IDC20A Debug Probe

OVERVIEW

The Industry Standard for Almost Every Embedded Platform

The IDC20A debug probe was originally designed to debug SoCs with an Arm® CoreSight™ debug infrastructure. Due to the enormous success of the Arm architecture, this debug concept became the de-facto debug standard for multicore systems in the embedded market.

Today the IDC20A debug probe supports various of architectures and protocols to debug SoCs with and without CoreSight™ and is Lauterbach’s most successful debug probe.

BENEFITS

Your Fast and Reliable Debug Probe for Almost Any Project

The IDC20A Debug Probe has been designed for maximum flexibility. Featuring the most common pin-out in the whole embedded market with a wide input voltage range and excellent signal integrity, it is a perfect fit for a large number of targets from general industrial applications to high-speed mobile device designs.

Supports even the most heterogeneous chips

When debugging multicore-systems, it becomes essential that the debug probe is able to concurrently control cores of various architectures within one SoC. The IDC20A Debug Probe provides this flexibility and supports a wide range of architectures.

Perfect fit for almost any target

The IDC20A Debug Probe provides the most common pin-out in the embedded market. Together with a large selection of adapters it is the perfect fit for a wide range of targets.

High transfer speed and signal integrity

With transceivers located close to the target, the IDC20A Debug Probe provides highest signal integrity at highest transfer speeds. For appropriate processors the high throughput performance even allows some real time tracing.

Wide Voltage Range starting from 0.4V

Supports high-speed targets with low I/O voltages down to 0.4 V as well as standard industrial applications with I/O voltages up to 5V.

SUPPORTED ARCHITECTURES

Get Control of Almost Any Chip

The IDC20A is a standard debug probe for a number of industries including mobile communications, medical, consumer electronics, semiconductors, aerospace, industrial and others. It supports dozens of architectures, from today's established microarchitectures to trendy new architectures. IDC20A covers chips from tiny microcontrollers to the most complex SoCs, Soft-Cores (implemented in FPGAs) and various sub-controllers like DSPs.

Arm/Cortex

AndesCore

APEX

APS3

ARC

AVR8

ARP32

Beyond

C166SV2

C2000

C5000

C6000

C7000

CEVA-X

HC11

Hexagon

i8051

M32R

Universal Debug Protocol Support

JTAG (IEEE 1149.1)

JTAG is the debug protocol commonly available with most CPUs. Derived from Boundary Scan device test-ing, JTAG allows an external tool to communicate with a Test Access Point (TAP) controller inside a chip. A TAP is the access point to the debug infrastructure within a chip. TAPs can be chained to allow the debug-ging of several cores via a single debug probe.

cJTAG (compact JTAG) (IEEE 1149.7)

A technology based on JTAG which reduces the pin count of the debug interface and is optimized for accessing multiple cores in a star topology. It allows the integration of more and more cores in the future without having to change interfaces or principles. cJTAG uses a 2-wire interface.

SWD/SWO

SWD (Serial Wire Debug) is a 2-pin debug interface defined by Arm®, which is optimized to access the CoreSight™ debug infrastructure with maximum performance. Serial Wire Output (SWO) is an optional extension pin to SWD. If a processor has an SWO pin, the IDC20A debug probe is able to receive trace data from both code instrumentation and data accesses*.

*Supported by PowerDebug E40/PowerDebug Pro and newer base modules

Renesas Single-Wire UART

RL78 processors are debugged via a UART like 1-line debug interface using the pins RESET and TOOL0, while the older 78K0R processors use an additional signal TOOL1.

UPDI

The Unified Program and Debug Interface (UPDI) designed by Microchip is a proprietary protocol to debug and program tinyAVR® and megaAVR® devices through a single pin, which is also the chip’s reset pin. These devices can also be programmed via a Serial Peripheral Interface (SPI).

Andes Serial Debug Port

Serial Debug Port is a two-wire option for AndesCore™ and RISC-V processors designed by Andes Technology.

TECHNICAL DATA

Technical Information for the IDC20A Debug Probe

Voltage Range	From 0.4V to 5.0 V
Debug Clock Frequency	From 10 kHz to 100 MHz

Pinout specification

ORDER INFORMATION

Get the IDC20A Probe for Your Architecture

Debugger Cortex-M (Armv6/7/8) IDC20A (PACK)

Supports Arm Cortex-M cores and SecurCore SC000/SC300 trace support ETM Cortex-M via ETB included GTM and IPU debugging included IDC20A debug cable supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port, (0.4V - 5V) includes software for Windows, Linux and MacOSX cJTAG and SWD require Power Debug Interface USB 2.0/USB 3.0, Power Debug Ethernet, PowerTrace, Power Debug II PowerDebug PRO, PowerDebug E40 or PowerDebug X50

Product number: LA-3254