Search results for "la-3791"

Floating license to use the TRACE32 Instruction Set Simulator for automated tests via script language PRACTICE or via the TRACE32 Remote API Supports Intel x86/x64 For Windows, Linux, and macOS. Floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

License for debugging the Cortex-A/R Armv7 architecture via Generic Transactor Library for Windows and Linux for RTL emulation or RTL simulation requires that EDA partner supports GTL interface floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

License for debugging the Cortex-A/R (Armv8/v9) architecture via "Software Debugging over Arm CoreSight Wire Protocol (CSWP)" Floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ) The TRACE32 software must be specially adapted from Lauterbach for each chip. Please contact the Lauterbach development department before ordering.

License for debugging the Xtensa architecture via Tessent Embedded Analytics (former UltraSoC) USB Debug for Windows and Linux requires TRACE32 software R.2022.02 The TRACE32 software must be specially adapted from Lauterbach for each chip. Please contact the Lauterbach development departement before ordering. floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

License to use TRACE32 PowerView Front-End TRACE32 PowerView Front-End can be used to connect to third-party solutions such as: - virtual target/simulators - target server such as GDB For details please refer to tool chain support list for your core architecture supports Arm based architectures floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

License for debugging the Cortex-M architecture (Armv6/7/8 32-bit) via Tessent Embedded Analytics (former UltraSoC) USB Debug for Windows and Linux requires TRACE32 software R.2020.09 The TRACE32 software must be specially adapted from Lauterbach for each chip. Please contact the Lauterbach development departement before ordering. floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

License for debugging the RISC-V 64-bit architecture via Tessent Embedded Analytics (former UltraSoC) USB Debug for Windows and Linux requires TRACE32 software R.2020.09 The TRACE32 software must be specially adapted from Lauterbach for each chip. Please contact the Lauterbach development departement before ordering. floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

License for debugging the Cortex-A V7 architecture (32-bit) via Tessent Embedded Analytics (former UltraSoC) USB Debug for Windows and Linux requires TRACE32 software R.2020.09 The TRACE32 software must be specially adapted from Lauterbach for each chip. Please contact the Lauterbach development departement before ordering. floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

Converter from IDC20A to 12 pin PMOD connectors with the JTAG pinout from SiFive. The adapter exists in two variants: with male and female PMOD connector. This adapter has the male PMOD connector. PMOD is an open standard defined by Digilent for peripherals used with FPGAs or microcontrollers. The PMOD pinout of this adapter does ONLY work with targets that use the pinout that was defined by SiFive. So it is not a general/official RISC-V pinout. In case of FPGA boards, the pinout may depend on the used FPGA image.

Converter from Intel MIPI60-Cv2 to MIPI34 pin-out on target Converts termination scheme Intel (50 Ohm parallel termination at receiver) to termination scheme ARM (50 Ohm series termination at sender) Support for JTAG/SWD Maps Intel specific debug signals to MIPI34 pins. Default mapping: Intel PREQ -> DBGREQ (pin 18 on MIPI34) Intel PRDY -> DBGACK (pin 20 on MIPI34) Intel HOOK6 (PMODE) -> RTCK (pin 12 on MIPI34) Intel HOOK0 (PowerGood) -> BCE (pin 14 on MIPI34) Intel HOOK7 (ResetOut) -> RESET (pin 10 on MIPI34) TVREF (trace reference voltage) == DVREF (debug reference voltage) For other possible options, please contact Lauterbach.