Search results for "cortex-m1"

TRACE32 Verilog Back-End for Cortex-M for RTL Simulations when the VPI interface is supported support for JTAG access Requires RLM floating license server Please add the RLM HostID of the license server to your order (please see our FAQ)

Supports Arm Arm Cortex-M cores and SecurCore SC000/SC300 trace support ETM Cortex-M included Only sold as part of a package for MicroTrace Cortex-M

License for debugging the Cortex-M architecture via Generic Transactor Library for Windows and Linux for RTL emulation or RTL simulation requires that EDA partner supports GTL interface floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

Supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port for Arm Cortex-M cores and SecurCore SC000/SC300 Bandwidth of 400 MBit/s per trace channel includes 256-MByte of trace RAM to support: - ITM via Serial Wire Output/TPIU - ETM Cortex-M continuous mode via TPIU (4-bit) Trace Streaming up to 100 MByte/s requires USB 3.0 (SuperSpeed) capable host computer Concurrent debugging of two or more Cortex-M cores requires a License for Multicore Debugging MicroTrace (LA-7960N) Can not be upgraded to include support for other core architectures

Supports Armv8 and Armv9 based Cortex-A, Cortex-R, Cortex-X and Neoverse 32/64-bit cores GTM, SPT, IPU and Multicore debugging included only suitable for debug cables newer than 08/2008 please add the serial number of the existing debug cable to your order

Supports Armv7-A/R based Cortex-A and Cortex-R 32-bit cores supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port (0.4 V - 5 V) includes software for Windows, Linux and MacOSX requires Power Debug Module cJTAG and SWD require Power Debug Interface USB 2.0/USB 3.0, Power Debug Ethernet, PowerTrace, Power Debug II or PowerDebug PRO

Supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port for Arm Cortex-M cores Bandwidth of 400 MBit/s per trace channel includes 256-MByte of trace RAM to support: - ITM via Serial Wire Output/TPIU - ETM Cortex-M continuous mode via TPIU (4-bit) Trace Streaming up to 100 MByte/s requires USB 3.0 (SuperSpeed) capable host computer Concurrent debugging of two or more Cortex-M cores requires a License for Multicore Debugging uTrace (LA-4534X)

License for debugging the Cortex-M architecture via "Software Debugging over XCP" protocol specified by ASAM e.V. as well as the ETAS-specific debugging protocol floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

Supports Arm Cortex-M cores and SecurCore SC000/SC300 trace support ETM Cortex-M via ETB included GTM and IPU debugging included IDC20A debug cable supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port, (0.4V - 5V) Includes software for Windows, Linux and macOS cJTAG and SWD require PowerDebug Interface USB 2.0/USB 3.0, PowerDebug Ethernet, PowerTrace, PowerDebug II PowerDebug PRO, PowerDebug E40 or PowerDebug X50

Supports Armv8-A/R or Armv9-A/R based Cortex-A and Cortex-R 32/64-bit cores IDC20A debug cable supports 5-pin standard JTAG, cJTAG and Serial Wire Debug Port, (0.4 V - 5 V) Multicore debugging included includes software for Windows, Linux and MacOSX requires Power Debug Module cJTAG and SWD require Power Debug Interface USB 2.0/USB 3.0, Power Debug Ethernet, PowerTrace, Power Debug II or PowerDebug PRO