Tessent Embedded Analytics Trace Solution for RISC-V


The embedded tools company
Trace Protocol
Pure Tessent Trace Infrastructure
RISC-V with Tessent Trace Components in an Arm CoreSight Trace Infrastructure
Generic TRACE32 Trace Features


Tessent Embedded Analytics RISC-V Trace
  Highlights
Compliant to Efficient Trace for RISC-V Version 1
Instruction trace
Data trace, if supported by the implemented trace IP
Timestamps, if supported by the implemented trace IP
Multicore tracing
Trace filters allow to reduce the generation of trace messages
Support for Tessent Embedded Analytics only trace infrastructure and Tessent Embedded Analytics trace IP integrated into an Arm CoreSight trace infrastructure
 
  Introduction
Siemens acquired UK-based UltraSoC Technologies Ltd. in July 2020. The UltraSoC product portfolio is now offered by Siemens EDA within its Tessent Software products under the name Tessent Embedded Analytics.




 

Trace Protocol


In its basic version, the Tessent Trace Encoder generates instruction execution details with optional timestamps compliant to the Efficent Trace for RISC-V Version 1. This is done non-intrusively, meaning that the real-time performance of the program is not affected. Timestamps are the only way to get time information for the onchip or the USB trace. If the trace is recorded with a TRACE32 Trace Module, the timestamps are generated by the module. A full-featured trace IP provides additionally data trace.
 

Pure Tessent Trace Infrastructure


The Tessent Embedded Analytics trace infrastructure IP can be integrated into any RISC-V based chip.


Support

TRACE32 Trace Tools

USB Protocol
  • TRACE32 RISC-V FrontEnd (floating license)
  • TRACE32 RISC-V Tessent 32-bit or 64-bit Debug BackEnd (floating license)
  • TRACE32 MultiCore License (floating license)
  • TRACE32 RISC-V Trace License (floating license)
 

RISC-V with Tessent Trace Components in an Arm CoreSight Trace Infrastructure


The Tessent Embedded Analytics trace infrastructure IP can be integrated into the CoreSight trace infrastructure.


Support

TRACE32 Trace Tools

Onchip Trace (ETB/ETF)
  • TRACE32 Debug Module.
  • TRACE32 Debug Cable with RISC-V 32-bit or 64-bit debug license and
    RISC-V trace license
Off-chip Trace Port (HSSTP)

Adaptation for CoreSight HSSTP

 

Generic TRACE32 Trace Features


Trace-based Debugging (CTS)
  • Allows re-debuggging of a traced program section
  • Provides forward and backward debugging capabilities
  • High-level language trace display including all local variables
  • Timing and function nesting display
  • Has the ability to fill most trace gaps caused by the limited bandwidth of trace port

Trace-based Profiling
  • Detailed analysis of function run-times
  • Detailed analysis of task run-times and state
  • Graphical analysis of variable values over the time
  • Analysis of the time interval of a single event (e.g. Interrupt)
  • Analysis of the time interval between 2 defined events

Trace-based Code Coverage
  • Real-time code coverage without instrumentation
  • Suitable for long-term testing
  • Support for all common code coverage metrics
  • Automated report generation
  • Full support of multicore chips





Copyright © 2021 Lauterbach GmbH, Altlaufstr.40, 85635 Höhenkirchen-Siegertsbrunn, Germany   Impressum     Privacy Policy
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 07-Jun-2021