In its basic version, the Tessent Trace Encoder generates instruction execution details with optional timestamps compliant to the Efficent Trace for RISC-V Version 1.
This is done non-intrusively, meaning that the real-time performance of the program is not affected. Timestamps are the only way to get time information for the onchip or the USB trace.
If the trace is recorded with a TRACE32 Trace Module, the timestamps are generated by the module.
A full-featured trace IP provides additionally data trace.
Pure Tessent Trace Infrastructure
The Tessent Embedded Analytics trace infrastructure IP can be integrated into any RISC-V based chip.
 TRACE32 Trace Tools
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USB Protocol
- TRACE32 RISC-V FrontEnd (floating license)
- TRACE32 RISC-V Tessent 32-bit or 64-bit Debug BackEnd (floating license)
- TRACE32 MultiCore License (floating license)
- TRACE32 RISC-V Trace License (floating license)
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RISC-V with Tessent Trace Components in an Arm CoreSight Trace Infrastructure
The Tessent Embedded Analytics trace infrastructure IP can be integrated into the CoreSight trace infrastructure.
TRACE32 Trace Tools
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Onchip Trace (ETB/ETF)
- TRACE32 Debug Module.
- TRACE32 Debug Cable with RISC-V 32-bit or 64-bit debug license and
RISC-V trace license
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Off-chip Trace Port (HSSTP)
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Generic TRACE32 Trace Features
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- Allows re-debuggging of a traced program section
- Provides forward and backward debugging capabilities
- High-level language trace display including all local variables
- Timing and function nesting display
- Has the ability to fill most trace gaps caused by the limited bandwidth of trace port
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- Detailed analysis of function run-times
- Detailed analysis of task run-times and state
- Graphical analysis of variable values over the time
- Analysis of the time interval of a single event (e.g. Interrupt)
- Analysis of the time interval between 2 defined events
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- Real-time code coverage without instrumentation
- Suitable for long-term testing
- Support for all common code coverage metrics
- Automated report generation
- Full support of multicore chips
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Trace Protocol
