Sifive cores use a Nexus 5001 compliant trace protocol. Supported instruction trace formats are:
- Nexus Branch Trace Messages (BTM)
- Nexus Branch History Trace Messages (HTM)
Both message types can optionally contain a timestamp field. These timestamps are the only way to get time information for the onchip trace.
If the trace is recorded with a TRACE32 Trace Module, the Nexus Messages receive their timestamps by the tool.
Trace Infrastructure for Chips with only SiFive RISC-V Cores
This is a proprietary SiFive solution, both the cores and the trace infrastructure must be SiFive.
 TRACE32 Trace Tools
SiFive RISC-V Cores in an Arm CoreSight Trace Infrastructure
The SiFive Core and the corresponding SiFive Nexus Trace Encoder can also be integrated into the CoreSight trace infrastructure.
TRACE32 Trace Tools
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Onchip Trace (ETB/ETF)
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Off-chip Trace Port (TPIU)
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- Allows re-debuggging of a traced program section
- Provides forward and backward debugging capabilities
- High-level language trace display including all local variables
- Timing and function nesting display
- Has the ability to fill most trace gaps caused by the limited bandwidth of trace port
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- Detailed analysis of function run-times
- Detailed analysis of task run-times and state
- Graphical analysis of variable values over the time
- Analysis of the time interval of a single event (e.g. Interrupt)
- Analysis of the time interval between 2 defined events
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- Provides all metrics for functional safety
- For standard trace protocols TRACE32 Code Coverage gets by with no or very little instrumentation, full instrumentation as fallback
- Suitable for long-term testing
- Automated report generation in multiple exchange formats
- TRACE32 Trace-Based Code Coverage is included in the scope of delivery of all TRACE32 Debug & Trace Tools at no additional cost
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Trace Protocol
