Proprietary SiFive Nexus Trace Solution for RISC-V

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Trace Protocol
Trace Infrastructure for Chips with only SiFive RISC-V Cores
SiFive RISC-V Cores in an Arm CoreSight Trace Infrastructure
Generic Trace Features

SiFive RISC-V Trace
SiFive cores only
Based on Nexus message protocol
Instruction trace
Trace protocol may include timestamps
Multicore tracing
Support for pure SiFive trace infrastructure or SiFive trace IP integrated into an Arm CoreSight trace infrastructure


Trace Protocol

Sifive cores use a Nexus 5001 compliant trace protocol. Supported instruction trace formats are:
  • Nexus Branch Trace Messages (BTM)
  • Nexus Branch History Trace Messages (HTM)
Both message types can optionally contain a timestamp field. These timestamps are the only way to get time information for the onchip trace. If the trace is recorded with a TRACE32 Trace Module, the Nexus Messages receive their timestamps by the tool.

Trace Infrastructure for Chips with only SiFive RISC-V Cores

This is a proprietary SiFive solution, both the cores and the trace infrastructure must be SiFive.


TRACE32 Trace Tools

Onchip Trace (SRAM)

SiFive RISC-V Cores in an Arm CoreSight Trace Infrastructure

The SiFive Core and the corresponding SiFive Nexus Trace Encoder can also be integrated into the CoreSight trace infrastructure.


TRACE32 Trace Tools

Onchip Trace (ETB/ETF) Off-chip Trace Port (TPIU)

Target Adaptation for Arm CoreSight TPIU


Generic Trace Features

Trace-based Debugging (CTS)
  • Allows re-debuggging of a traced program section
  • Provides forward and backward debugging capabilities
  • High-level language trace display including all local variables
  • Timing and function nesting display
  • Has the ability to fill most trace gaps caused by the limited bandwidth of trace port

Trace-based Profiling
  • Detailed analysis of function run-times
  • Detailed analysis of task run-times and state
  • Graphical analysis of variable values over the time
  • Analysis of the time interval of a single event (e.g. Interrupt)
  • Analysis of the time interval between 2 defined events

Trace-based Code Coverage
  • Real-time code coverage without instrumentation
  • Suitable for long-term testing
  • Support for all common code coverage metrics
  • Automated report generation
  • Full support of multicore chips

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Last generated/modified: 07-Jan-2021