Xtensa Debugger


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IDE - Integrated Development Environment
Adaptation
Details and Configurations


Xtensa Debugger
  Highlights
Full high-level and assembler debugging
Batch Processing
Support for Internal Triggers
Unlimited Software Breakpoints
Target voltage 0.4 .. 5.0 V
Core Reset detection
Little- and Big-Endian support
Fast download (ETHERNET, PARALLEL, USB)


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Product
Information
Support
Technical Support
[ip.cadence.com]  Tensilica IP Page at cadence


Demo Software for Download



Full Memory Access

  • Display/Read/Write of target memory
  • Set/Delete Breakpoints
  • Full access to Auxiliary memory space

Variable Debug Clock Speed

  • 10 kHz...50 MHz
  • about 2/3 core clock
  • Variable up to 100 MHz (PowerDebug only)

High-Speed Download

  • 50 KByte/sec @ 12MHz core clock

 

IDE - Integrated Development Environment


 

Adaptation


Adaptation for Xtensa

Half-Size Adapters for Debuggers
  • 100 mil to 50 mil Adapters
  • Small Footprint for Target Connector

 

Details and Configurations






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The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 03-Dec-2019