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- 100 mil to 50 mil Adapters
- Small Footprint for Target Connector
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 C
- CARH850 (RENESAS)
- ELF/NEC
- VX-RH850 (TASKING)
- ELF/DWARF
C/C++
- GREENHILLS-C (GREENHILLS)
- ELF/DWARF
- ICCRH850 (IAR)
- UBROF
- CUBESUITE+ (RENESAS)
- ELF
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More TRACE32 Tools for RH850
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- Front-end to third-party virtual targets
- Front-end to third-party core simulators
- Front-end to third-party target servers
- Front-end to TRACE32 Back-End
- Same GUI as TRACE32 hardware debuggers
- Debug features as provided by third-party software/TRACE32 Back-End
- Trace features as provided by third-party software/TRACE32 Back-End
- Windows, Linux and MacOSX
- Reprise RLM floating licenses
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- Program flow via Branch Trace Messages (BTM)
- Data Trace Messaging supported (DTM)
- Supports onchip peripheral block tracing
- Multicore tracing
- Trace-based debugging
- Full support for trigger and filter features
- Up to 8 GByte trace memory
- 5 ns off-chip time stamp
- Comprehensive program profiling
- Target-OS aware profiling
- AUTOSAR-aware profiling
- Code coverage
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- 4 GByte trace memory
- Universal module that is prelicensed for a trace protocol on delivery, additional trace protocol licenses can be added
- Aurora-based trace protocols up to 8 RX lanes, up to 12.5 Gbit/s per lane
- Speed booster TRACE32 Preprocessor Aurora 2 delivers up to 22.5 Gbit/s per lane for up to 4 lanes
- PCIe 3.0-based trace protocol up to 8 RX/TX lanes, up to 8 Gbit/s per lane
- Maximum bandwidth of 100 GBit/s
- Reference-clock and bit-clock support
- Fast trace upload to the host computer
- Support for TRACE32 Streaming up to 400 MByte/s
- TRACE32 Standard Probe/Analog Probe option
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- Debugger for all cores of a multicore chip / multiprocessor system
- Debugging of high-performance and real-time cores, DSPs, accelerator and special-purpose cores
- Support for every multicore topology
- Support for all multicore operation modes
- Support for AMP, iAMP and SMP systems
- Single debug hardware can be licensed for all cores of a multicore chip / multiprocessor system
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- Real-time, non-intrusive display of RTOS system resources
- Task stack coverage
- Task related breakpoints
- Task context display
- SMP support
- Task related performance measurement
- Statistic evaluation and graphic display of task run times
- Task related evaluation of function run times
- PRACTICE functions for OS data
- Easy access via RTOS specific pull-down menus
- Support for all major RTOSes
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- ORTI and ARTI compliant
- Single-core and SMP operating systems
- Support for all standard AUTOSAR providers such as Elektrobit, ETAS, Vector
- Concurrent debugging of multiple AUTOSAR Classic platforms
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- Seamless debugging of the total system in stop-mode
- Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
- Hypervisor-aware debugging for high-performance cores (MMU) such as Arm Cortex, PowerArchitecture and Intel x64
- Hypervisor-aware debugging for selected real-time cores (MPU) such as Arm Cortex-R52/-R82, RH850 (G4MH4 core and later) and TriCore TC4x
- Machine ID allows the user to uniquely identify any virtual machine in the system
- Machine ID provides full visibility of context of active and inactive virtual machines
- OS-awareness can be loaded for each virtual machine
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- Structured Language
- Menu Support
- Command Logs
- Custom Menues
- Custom Toolbars and Buttons
- Custom Dialog Windows
- 64-Bit Arithmetic
- Numeric, Logical and String Operators
- Direct Access to System States
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Flyer: Multicore Debug and Trace for RH850
Adaptation
