Search results for "risc-v"

TRACE32 Back-End License to debug 32 bit RISC-V cores (RV32) on RTL Simulations using the Verilog Procedural Interface Interface (VPI). Only JTAG via VPI is supported. Requires a RISC-V Front-End license (LA-8910L) Requires RLM floating license server. Please add the RLM HostID of the license server to your order.

Trace recorder for serial high-speed ports with 4 Gigabyte trace memory for RISC-V Tested for SiFive Nexus IP. Tested for Tessent Embedded Analytics (aka. UltraSoC) encoder IP Other IP on request. Records up to 8 lanes with 12.5 Gbit/s per lane (more with opt. Prepro.) Voltage range: 0.15 to 1.25 differential voltage. Requires accessory kit LA-3521 or LA-3522. Requires PowerDebug X50, PowerDebug PRO, or PowerDebug II. Requires PC with USB 3 or Gigabit Ethernet, 4 GB RAM min, and 64-bit OS.

Trace recorder for serial high-speed ports with 8 Gigabyte trace memory for RISC-V Tested for SiFive Nexus IP. Tested for Tessent Embedded Analytics (aka. UltraSoC) encoder IP Other IP on request. Records up to 8 lanes with 12.5 Gbit/s per lane (more with opt. Prepro.) Voltage range: 0.15 to 1.25 differential voltage. Requires accessory kit LA-3521 or LA-3522. Requires PowerDebug X50, PowerDebug PRO, or PowerDebug II. Requires PC with USB 3 or Gigabit Ethernet, 4 GB RAM min, and 64-bit OS.

Supports eSi-RISC Core Includes software for Windows, Linux and macOS Requires PowerDebug module Debug cable with 16 pin connector Voltage range 1.8V to 3.6V

License for debugging the RISC-V 32-bit architecture via Generic Transactor Library for Windows and Linux requires TRACE32 software R.2020.09 for RTL emulation or RTL simulation requires that EDA partner supports GTL interface floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

License for debugging the RISC-V 64-bit architecture via Generic Transactor Library for Windows and Linux requires TRACE32 software R.2020.09 for RTL emulation or RTL simulation requires that EDA partner supports GTL interface floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

License for debugging the RISC-V 32-bit architecture via Tessent Embedded Analytics (former UltraSoC) USB Debug for Windows and Linux requires TRACE32 software R.2020.09 The TRACE32 software must be specially adapted from Lauterbach for each chip. Please contact the Lauterbach development departement before ordering. floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

License for debugging the RISC-V 64-bit architecture via Tessent Embedded Analytics (former UltraSoC) USB Debug for Windows and Linux requires TRACE32 software R.2020.09 The TRACE32 software must be specially adapted from Lauterbach for each chip. Please contact the Lauterbach development departement before ordering. floating license via RLM (Reprise License Manager) Please add the RLM HostID of the license server to your order (please see our FAQ)

Converter from IDC20A connector to Altera 10-pin (Byteblaster) or RISC-V 10-pin Target connector pitch can be 2.54mm or 1.27mm (half size)

Program flow trace for TriCore OCDS Level2 to Samtec 60 connector, cable and software 130 MHz clock speed, 3.0 - 5.5 V 2 x RISC-Trace-Depth converter LA-7927 required for AMP40 connection