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- Debugger for all cores of a multicore chip / multiprocessor system
- Debugging of high-performance and real-time cores, DSPs, accelerator and special-purpose cores
- Support for every multicore topology
- Support for all multicore operation modes
- Support for AMP, iAMP and SMP systems
- Single debug hardware can be licensed for all cores of a multicore chip / multiprocessor system
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- Full integrated support of processor's MMU
- Display of processor MMU registers
- Display of MMU table entries
- Display of address translation table
- 'Shadowing' MMU address translation inside debugger
- Full virtual and physical access to target at any time
- Debugger has optionally write access to write protected memory areas
- Detection and decoding of software MMU tables built by operating systems
- Support for several user space MMU tables side by side
- TLB context tracking and git statistics via CTS
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- Real-time, non-intrusive display of RTOS system resources
- Task stack coverage
- Task related breakpoints
- Task context display
- SMP support
- Task related performance measurement
- Statistic evaluation and graphic display of task run times
- Task related evaluation of function run times
- PRACTICE functions for OS data
- Easy access via RTOS specific pull-down menus
- Support for all major RTOSes
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- Seamless debugging of the total system in stop-mode
- Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
- Hypervisor-aware debugging for high-performance cores (MMU) such as Arm Cortex, PowerArchitecture and Intel x64
- Hypervisor-aware debugging for selected real-time cores (MPU) such as Arm Cortex-R52/-R82, RH850 (G4MH4 core and later) and TriCore TC4x
- Machine ID allows the user to uniquely identify any virtual machine in the system
- Machine ID provides full visibility of context of active and inactive virtual machines
- OS-awareness can be loaded for each virtual machine
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- Single-core and SMP operating systems
- Debug support for standard rich OSes such a eMCOS. Linux, PikeOS, QNX
- Standardized, OS-independent list display of AUTOSAR Adaptive Applications
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- Structured Language
- Menu Support
- Command Logs
- Custom Menues
- Custom Toolbars and Buttons
- Custom Dialog Windows
- 64-Bit Arithmetic
- Numeric, Logical and String Operators
- Direct Access to System States
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- Compatible to external ETM Trace
- Readout through JTAG
- No Speed Limit
- Full Trace of Code and Data
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- Up to 8 GByte trace buffer
- Target voltage 1.2 .. 3.3 V
- 5 ns time stamp
- Program and data trace
- Performance analysis
- Function and task run-time measurement
- AUTOSAR-aware profiling
- Code coverage
- Support for Embedded Trace Macrocell (ETM), Program Trace Macrocell (PTM)
- Support for Embedded Trace Buffer (ETB), Trace Memory Controller (TMC), Trace Port Interface Unit (TPIU)
- Support for multiple trace sources in a single stream (CoreSight trace)
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- Support of High-Speed Serial Trace Port (ETM-HSSTP, ARM specified)
- Compatible to Xilinx Aurora protocol
- Support of up to four differential lanes
- Maximum 6,25Gbit/s lane speed
- Up to 8 GByte trace buffer size, sufficient for up to 48 Giga CPU cycles
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- 4 GByte trace memory
- Universal module that is prelicensed for a trace protocol on delivery, additional trace protocol licenses can be added
- Aurora-based trace protocols up to 8 RX lanes, up to 12.5 Gbit/s per lane
- Speed booster TRACE32 Preprocessor Aurora 2 delivers up to 22.5 Gbit/s per lane for up to 4 lanes
- PCIe 3.0-based trace protocol up to 8 RX/TX lanes, up to 8 Gbit/s per lane
- Maximum bandwidth of 100 GBit/s
- Reference-clock and bit-clock support
- Fast trace upload to the host computer
- Support for TRACE32 Streaming up to 400 MByte/s
- TRACE32 Standard Probe/Analog Probe option
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[www.arm.com] CoreSight On-chip Debug & Trace IP
Adaptation
