Cortex-A Armv7 Debugger


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Adaptation
TRACE32 Debug Features
Trace Tools


Cortex-A  Armv7 Debugger
  Highlights
Multicore debugging
Interface to all compilers
OS awareness debugging
AUTOSAR aware debugging
Display of internal and external peripherals at a logical level
Flash programming
Powerful script language
Support for CoreSight components like Debug Access Port, Trace Funnel, Trace Port Interface Unit, Embedded Trace Buffer, Cross Trigger Interface, Cross Trigger Matrix, System Trace Port, Trace Memory Controller
Real-time access to system memory and peripheral registers through Debug Access Port without halting the core
Multiprocessor debugging
Software compatible to all TRACE32 tools
High-Speed download
 AD, ALLWINNER, ARM, BROADCOM, CORTINA, HILSCHER, INFINEON, INTEL, LSI, MARVELL, MICROCHIP, NANOXPLORE, NVIDIA, NXP, QUALCOMM, RENESAS, ROCKCHIP, SAMSUNG, SILICONMOBILITY, SOCIONEXT, STM, TELECHIPS, TI, XILINX



Link Support
Technical Support
[www.arm.com]  CoreSight On-chip Debug & Trace IP
Video: Synchronized AMP Debugging with ARMĀ® and NiosĀ®-II




 

Adaptation


Adaptation for ARM Debug Connector

Target Adaptation for MIPI-10/-20T

 

TRACE32 Debug Features


Multicore Debugging
  • Debugger for all cores of a multicore chip
  • Debugging of application cores, DSPs, accelerator cores and special-purpose cores
  • Debugging of more than 80 core architectures
  • Support for every multicore topology
  • Support for all multicore operation modes
  • Support for AMP and SMP systems
  • Single debug hardware can be licensed for all cores of a multicore chip

MMU Support
  • Full integrated support of processor's MMU
  • Display of processor MMU registers
  • Display of MMU table entries
  • Display of address translation table
  • 'Shadowing' MMU address translation inside debugger
  • Full virtual and physical access to target at any time
  • Debugger has optionally write access to write protected memory areas
  • Detection and decoding of software MMU tables built by operating systems
  • Support for several user space MMU tables side by side
  • TLB context tracking and git statistics via CTS

OS-aware Debugging
  • Real-time, non-intrusive display of RTOS system resources
  • Task stack coverage
  • Task related breakpoints
  • Task context display
  • SMP support
  • Task related performance measurement
  • Statistic evaluation and graphic display of task run times
  • Task related evaluation of function run times
  • PRACTICE functions for OS data
  • Easy access via RTOS specific pull-down menus
  • Support for all major RTOSes

Hypervisor-aware Debugging
  • Seamless debugging of the total system in stop-mode
  • Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
  • Machine ID allows the user to uniquely identify any virtual machine in the system
  • Machine ID provides full visibility of context of active and inactive virtual machines
  • OS-awareness can be loaded for each virtual machine

AUTOSAR-Aware Debugging: Adaptive Platform
  • Single-core and SMP operating systems
  • Debug support for standard rich OSes such a eMCOS. Linux, PikeOS, QNX
  • Standardized, OS-independent list display of AUTOSAR Adaptive Applications

Script Language PRACTICE
  • Structured Language
  • Menu Support
  • Command Logs
  • Custom Menues
  • Custom Toolbars and Buttons
  • Custom Dialog Windows
  • 64-Bit Arithmetic
  • Numeric, Logical and String Operators
  • Direct Access to System States

 

Trace Tools


ETB Trace
  • Compatible to external ETM Trace
  • Readout through JTAG
  • No Speed Limit
  • Full Trace of Code and Data

Off-chip Parallel Trace
  • Up to 8 GByte trace buffer
  • Target voltage 1.2 .. 3.3 V
  • 5 ns time stamp
  • Program and data trace
  • Performance analysis
  • Function and task run-time measurement
  • AUTOSAR-aware profiling
  • Code coverage
  • Support for Embedded Trace Macrocell (ETM), Program Trace Macrocell (PTM)
  • Support for Embedded Trace Buffer (ETB), Trace Memory Controller (TMC), Trace Port Interface Unit (TPIU)
  • Support for multiple trace sources in a single stream (CoreSight trace)

Off-chip Serial Trace via Serial Preprocessor
  • Support of High-Speed Serial Trace Port (ETM-HSSTP, ARM specified)
  • Compatible to Xilinx Aurora protocol
  • Support of up to four differential lanes
  • Maximum 6,25Gbit/s lane speed
  • Up to 8 GByte trace buffer size, sufficient for up to 48 Giga CPU cycles

Off-chip Serial Trace via PowerTrace Serial
  • 4 GByte trace memory
  • Universal module that is prelicensed for a trace protocol on delivery
  • Additional trace protocol licenses can be added
  • Up to 12.5 Gbit/s per lane
  • Maximum bandwidth of 100 GBit/s
  • Aurora-based trace protocols up to 8 RX lanes
  • PCIe 3.0-based trace protocol up to 8 RX/TX lanes
  • Reference-clock and bit-clock support
  • Fast trace upload to the host computer
  • Support for TRACE32 Streaming up to 400 MByte/s
  • TRACE32 Standard Probe option
  • TRACE32 Analog Probe option





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Last generated/modified: 11-May-2022