IDE - Integrated Development Environment
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- Compatible to external ETM Trace
- Readout through JTAG
- No Speed Limit
- Full Trace of Code and Data
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- Up to 4 GByte trace buffer
- Target voltage 1.2 .. 3.3 V
- 5 ns time stamp
- Program and data trace
- Performance analysis
- Function and task run-time measurement
- Code coverage
- Support for Embedded Trace Macrocell (ETM), Program Trace Macrocell (PTM)
- Support for Embedded Trace Buffer (ETB), Trace Memory Controller (TMC), Trace Port Interface Unit (TPIU)
- Support for multiple trace sources in a single stream (CoreSight trace)
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- Support of High-Speed Serial Trace Port (ETM-HSSTP, ARM specified)
- Compatible to Xilinx Aurora protocol
- Support of up to four differential lanes
- Maximum 6,25Gbit/s lane speed
- Up to 4 GByte trace buffer size, sufficient for up to 24 Giga CPU cycles
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- 4 GByte trace memory
- Universal module that is prelicensed for a trace protocol on delivery
- Additional trace protocol licenses can be added
- Up to 12.5 Gbit/s per channel
- Maximum bandwidth of 100 GBit/s
- Aurora-based trace protocols up to 8 RX lanes
- PCIe 3.0-based trace protocol up to 8 RX/TX lanes
- Reference-clock and bit-clock support
- Fast trace upload to the host computer
- Support for TRACE32 Streaming up to 180 MByte/s, compression allows higher data rates to be achieved
- PODBUS Express interface to PowerDebug PRO
- PODBUS and PODBUS Express interfaces to Logic Analyzer modules, e.g. PowerProbe, PowerIntegrator
- Additional independent 17 channel logic analyzer (with included Standard Probe)
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Details and Configurations
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[www.arm.com] CoreSight On-chip Debug & Trace IP
