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- Front-end to third-party virtual targets
- Front-end to third-party core simulators
- Front-end to third-party target servers
- Front-end to TRACE32 Back-End
- Same GUI as TRACE32 hardware debuggers
- Debug features as provided by third-party software/TRACE32 Back-End
- Trace features as provided by third-party software/TRACE32 Back-End
- Windows, Linux and MacOSX
- Reprise RLM floating licenses
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- Compatible to external ETM Trace
- Readout through JTAG
- No Speed Limit
- Full Trace of Code and Data
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- Up to 8 GByte trace buffer
- Target voltage 1.2 .. 3.3 V
- 5 ns time stamp
- Program and data trace
- Performance analysis
- Function and task run-time measurement
- Code coverage
- Support for Embedded Trace Macrocell (ETM), Program Trace Macrocell (PTM)
- Support for Embedded Trace Buffer (ETB), Trace Memory Controller (TMC), Trace Port Interface Unit (TPIU)
- Support for multiple trace sources in a single stream (CoreSight trace)
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- Support of High-Speed Serial Trace Port (ETM-HSSTP, ARM specified)
- Compatible to Xilinx Aurora protocol
- Support of up to four differential lanes
- Maximum 6,25Gbit/s lane speed
- Up to 8 GByte trace buffer size, sufficient for up to 48 Giga CPU cycles
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- 4 GByte trace memory
- Universal module that is prelicensed for a trace protocol on delivery
- Additional trace protocol licenses can be added
- Up to 12.5 Gbit/s per lane
- Maximum bandwidth of 100 GBit/s
- Aurora-based trace protocols up to 8 RX lanes
- PCIe 3.0-based trace protocol up to 8 RX/TX lanes
- Reference-clock and bit-clock support
- Fast trace upload to the host computer
- Support for TRACE32 Streaming up to 400 MByte/s
- TRACE32 Standard Probe option
- TRACE32 Analog Probe option
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- Debugger for all cores of a multicore chip
- Debugging of application cores, DSPs, accelerator cores and special-purpose cores
- Debugging of more than 80 core architectures
- Support for every multicore topology
- Support for all multicore operation modes
- Support for AMP and SMP systems
- Single debug hardware can be licensed for all cores of a multicore chip
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- Display of onchip peripherals
- User definable windows
- Interactive window definition with softkey support
- Pulldown menues for selection of choices
- Additional description for each field
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- Optimum flash programming performance
- Support for all file formats
- Ready-to-run flash scripts
- Ready-to-use flash programming algorithms
- Dialog- or command-based programming as well as full scripting
- Full awareness of sensitive data
- Flash declaration via CFI
- Easy handling of different flash types on a target
- Software breakpoints in flash
- Simple code patching in flash
- Flash programming via boundary scan
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- Optimum flash programming performance
- Support for elf, Intel hex and S-record format
- Ready-to-use flash programming scripts
- Ready-to-use flash programming algorithms
- Memory dump for displaying the flash content
- Flash content can be easily copied and modified
- Flash programming via boundary scan (SPI, eMMC, I2C)
- Full programming access to spare area (NAND)
- Bad block treatment (NAND)
- ECC generation: Hamming, BCH, Reed-Solomon (NAND)
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- Supports multiple languages
- Full support for C++
- Integrated into TRACE32 environment
- Supports most compilers and hosts
- Same user interface on different hosts
- High speed download
- Debugs optimized code
- Display of function nesting
- Display of linked lists
- Powerful expression evaluation
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- Full integrated support of processor's MMU
- Display of processor MMU registers
- Display of MMU table entries
- Display of address translation table
- 'Shadowing' MMU address translation inside debugger
- Full virtual and physical access to target at any time
- Debugger has optionally write access to write protected memory areas
- Detection and decoding of software MMU tables built by operating systems
- Support for several user space MMU tables side by side
- TLB context tracking and git statistics via CTS
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- Real-time, non-intrusive display of RTOS system resources
- Task stack coverage
- Task related breakpoints
- Task context display
- SMP support
- Task related performance measurement
- Statistic evaluation and graphic display of task run times
- Task related evaluation of function run times
- PRACTICE functions for OS data
- Easy access via RTOS specific pull-down menus
- Support for all major RTOSes
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- Seamless debugging of the total system in stop-mode
- Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
- Machine ID allows the user to uniquely identify any virtual machine in the system
- Machine ID provides full visibility of context of active and inactive virtual machines
- OS-awareness can be loaded for each virtual machine
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- Long-time performance analysis for functions
- Long-time performance analysis for tasks
- Long-time analysis of the contents of a variable or memory location and more
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- Structured Language
- Menu Support
- Command Logs
- Custom Menues
- Custom Toolbars and Buttons
- Custom Dialog Windows
- 64-Bit Arithmetic
- Numeric, Logical and String Operators
- Direct Access to System States
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List of Supported Compilers
Adaptation
