Armv8 Cortex®-A, Cortex®-R and Cortex®-X Debugger


The embedded tools company
Adaptation
More TRACE32 Tools
TRACE32 Debug Features


Armv8  Debugger
  Highlights
Full support for all CoreSight components
Full architectural debug support

Support for 64-bit instruction set and 32-bit instruction sets ARM and THUMB
32-bit and 64-bit peripherals displayed on logical level
Support for 32-bit and 64-bit MMU formats
Auto-adaption of all display windows to AArch32/AArch64 mode

Ready-to-run FLASH programming scripts
Bare metal and OS-aware debugging
Hypvervisor-aware debugging for application cores and Cortex-R52/-R82
Multicore debugging
Seamless debugging of big.LITTLE systems based on Armv8
AMP debugging with DSPs, GPUs and other accelerator cores
Support for 32-bit and 64-bit semi-hosting
Other TRACE32 tools for ARMv8: Debugging of Virtual Targets, On-chip trace support (ETB, ETF, ETR), Off-chip trace tools (ETMv4)


Link
List of Supported Compilers
List of Supported Target Operating Systems
List of Supported Hypervisors
Ready-to-run bring-up scripts


[www.arm.com]  CoreSight On-chip Debug & Trace IP




 

Adaptation


Adaptation for Arm® Debug Connector

Target Adaptation for MIPI-10/-20T

 

More TRACE32 Tools


Debugging of Virtual Targets
  • Front-end to third-party virtual targets
  • Front-end to third-party core simulators
  • Front-end to third-party target servers
  • Front-end to TRACE32 Back-End
  • Same GUI as TRACE32 hardware debuggers
  • Debug features as provided by third-party software/TRACE32 Back-End
  • Trace features as provided by third-party software/TRACE32 Back-End
  • Windows, Linux and MacOSX
  • Reprise RLM floating licenses

On-Chip Trace (ETB, ETF, ETR)
  • Compatible to external ETM Trace
  • Readout through JTAG
  • No Speed Limit
  • Full Trace of Code and Data

Off-chip Parallel Trace (ETMv4)
  • Up to 8 GByte trace buffer
  • Target voltage 1.2 .. 3.3 V
  • 5 ns time stamp
  • Program and data trace
  • Performance analysis
  • Function and task run-time measurement
  • AUTOSAR-aware profiling
  • Code coverage
  • Support for Embedded Trace Macrocell (ETM), Program Trace Macrocell (PTM)
  • Support for Embedded Trace Buffer (ETB), Trace Memory Controller (TMC), Trace Port Interface Unit (TPIU)
  • Support for multiple trace sources in a single stream (CoreSight trace)

Off-chip Serial Trace via Serial Preprocessor (ETMv4)
  • Support of High-Speed Serial Trace Port (ETM-HSSTP, ARM specified)
  • Compatible to Xilinx Aurora protocol
  • Support of up to four differential lanes
  • Maximum 6,25Gbit/s lane speed
  • Up to 8 GByte trace buffer size, sufficient for up to 48 Giga CPU cycles

Off-chip Serial Trace via PowerTrace Serial (ETMv4)
  • 4 GByte trace memory
  • Universal module that is prelicensed for a trace protocol on delivery, additional trace protocol licenses can be added
  • Aurora-based trace protocols up to 8 RX lanes, up to 12.5 Gbit/s per lane
  • Speed booster TRACE32 Preprocessor Aurora 2 delivers up to 22.5 Gbit/s per lane for up to 4 lanes
  • PCIe 3.0-based trace protocol up to 8 RX/TX lanes, up to 8 Gbit/s per lane
  • Maximum bandwidth of 100 GBit/s
  • Reference-clock and bit-clock support
  • Fast trace upload to the host computer
  • Support for TRACE32 Streaming up to 400 MByte/s
  • TRACE32 Standard Probe/Analog Probe option

 

TRACE32 Debug Features


Multicore Debugging
  • Debugger for all cores of a multicore chip / multiprocessor system
  • Debugging of high-performance and real-time cores, DSPs, accelerator and special-purpose cores
  • Support for every multicore topology
  • Support for all multicore operation modes
  • Support for AMP, iAMP and SMP systems
  • Single debug hardware can be licensed for all cores of a multicore chip / multiprocessor system

MMU Support
  • Full integrated support of processor's MMU
  • Display of processor MMU registers
  • Display of MMU table entries
  • Display of address translation table
  • 'Shadowing' MMU address translation inside debugger
  • Full virtual and physical access to target at any time
  • Debugger has optionally write access to write protected memory areas
  • Detection and decoding of software MMU tables built by operating systems
  • Support for several user space MMU tables side by side
  • TLB context tracking and git statistics via CTS

OS-aware Debugging
  • Real-time, non-intrusive display of RTOS system resources
  • Task stack coverage
  • Task related breakpoints
  • Task context display
  • SMP support
  • Task related performance measurement
  • Statistic evaluation and graphic display of task run times
  • Task related evaluation of function run times
  • PRACTICE functions for OS data
  • Easy access via RTOS specific pull-down menus
  • Support for all major RTOSes

Hypervisor-aware Debugging
  • Seamless debugging of the total system in stop-mode
  • Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
  • Hypvervisor-aware debugging for high-performance cores (MMU) such as Arm Cortex, PowerArchitecture and Intel x64
  • Hypvervisor-aware debugging for selected real-time cores (MPU) such as Arm Cortex-R52/-R82, RH850 (G4MH4 core and later) and TriCore TC4x
  • Machine ID allows the user to uniquely identify any virtual machine in the system
  • Machine ID provides full visibility of context of active and inactive virtual machines
  • OS-awareness can be loaded for each virtual machine

AUTOSAR-Aware Debugging
  • Long-term commitment to AUTOSAR as active contributor
  • Debug support for AUTOSAR Classic and Adaptive Platform
  • Debug support for ORTI and ARTI
  • Longstanding close partnership with AUTOSAR providers
  • Concurrent debugging of AUTOSAR Classic and Adaptive Platform

Script Language PRACTICE
  • Structured Language
  • Menu Support
  • Command Logs
  • Custom Menues
  • Custom Toolbars and Buttons
  • Custom Dialog Windows
  • 64-Bit Arithmetic
  • Numeric, Logical and String Operators
  • Direct Access to System States





Copyright © 2022 Lauterbach GmbH, Altlaufstr.40, 85635 Höhenkirchen-Siegertsbrunn, Germany   Impressum     Privacy Policy
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 24-Nov-2022