Cortex-A/-R ARMv8 Debugger

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More TRACE32 Tools for ARMv8
TRACE32 Debug Features
Details and Configurations

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Cortex-A/-R  ARMv8  Debugger
Full support for all CoreSight components
Full architectural debug support

Support for 64-bit instruction set and 32-bit instruction sets ARM and THUMB
32-bit and 64-bit peripherals displayed on logical level
Support for 32-bit and 64-bit MMU formats
Auto-adaption of all display windows to AArch32/AArch64 mode

Ready-to-run FLASH programming scripts
Virtualization support
Bare metal and OS-aware debugging
Multicore debugging
Seamless debugging of big.LITTLE systems based on Cortex®-A57/Cortex®-A53, Cortex®-A72/Cortex®-A53, Cortex®-A73 or Cortex®-A35
AMP debugging with DSPs, GPUs and other accelerator cores
Support for 32-bit and 64-bit semi-hosting
Other TRACE32 tools for ARMv8: Debugging of Virtual Targets, On-chip trace support (ETB, ETF, ETR), Off-chip trace tools (ETMv4)
Support for
 88F3710, 88F3720, 88F7020, 88F7040, 88F8020, 88F8040, AM6526, AM6527, AM6528, AM6546, AM6548, APM883204-X1, APM883208-X1, APM883308-X1, APM883408-X1, APM883408-X2, BCM2837, BCM4908, BCM5871, CN80XX, CN81XX, CN83XX, CN88XX, CN913X, CN96XX, CN99XX, CORTEX-A32, CORTEX-A34, CORTEX-A35, CORTEX-A53, CORTEX-A55, CORTEX-A57, CORTEX-A65, CORTEX-A72, CORTEX-A73, CORTEX-A75, CORTEX-A76, CORTEX-A76AE, CORTEX-R52, DRA802M, DRA804M, E2V_LS1043A, E2V_LS1046A, E2V_LS1088A, E2V_LS2088A, EXYNOS5433, EXYNOS7420, EXYNOS7570, EXYNOS7580, EXYNOS7870, EXYNOS8890, EXYNOS8895, FALKOR, IMX8DUALX, IMX8MDUAL, IMX8MMINIQUAD, IMX8MQUAD, IMX8MQUADLITE, IMX8QUADX, IMX8QUADXPLUS, KIRIN620, KIRIN960, KRYO2XX, KRYOA, LS1012A, LS1023A, LS1026A, LS1028A, LS1043A, LS1046A, LS1088A, LS2044A, LS2048A, LS2080A, LS2084A, LS2088A, LX2080A, LX2120A, LX2160A, PXA1908, PXA1918, PXA1928, PXA1936, R8A77951, R8A77960, R8A77965, R8A77970, R8A77980, R8A77990, R8A77995, S32V234, S905, TEGRAX1, TEGRAX2, XAVIER, ZYNQ-ULTRASCALE+

Link Volt
Operation Voltage
Frequently Asked Questions
Technical Support
List of Supported Compilers
List of Supported Target Operating Systems
List of Supported Hypervisors
Ready-to-run bring-up scripts

[]  CoreSight On-chip Debug & Trace IP



Adaptation for ARM Debug Connector

Target Adaptation for MIPI-10/-20T/-20D/-34


More TRACE32 Tools for ARMv8

Debugging of Virtual Targets
  • Front-end to third-party virtual targets
  • Front-end to third-party core simulators
  • Front-end to third-party target servers
  • Front-end to TRACE32 Back-End
  • Same GUI as TRACE32 hardware debuggers
  • Debug features as provided by third-party software/TRACE32 Back-End
  • Trace features as provided by third-party software/TRACE32 Back-End
  • Windows, Linux and MacOSX
  • Reprise RLM floating licenses

On-Chip Trace (ETB, ETF, ETR)
  • Compatible to external ETM Trace
  • Readout through JTAG
  • No Speed Limit
  • Full Trace of Code and Data

Off-chip Parallel Trace (ETMv4)
  • Up to 4 GByte trace buffer
  • Target voltage 1.2 .. 3.3 V
  • 5 ns time stamp
  • Program and data trace
  • Performance analysis
  • Function and task run-time measurement
  • Code coverage
  • Support for Embedded Trace Macrocell (ETM), Program Trace Macrocell (PTM)
  • Support for Embedded Trace Buffer (ETB), Trace Memory Controller (TMC), Trace Port Interface Unit (TPIU)
  • Support for multiple trace sources in a single stream (CoreSight trace)

Off-chip Serial Trace via Serial Preprocessor (ETMv4)
  • Support of High-Speed Serial Trace Port (ETM-HSSTP, ARM specified)
  • Compatible to Xilinx Aurora protocol
  • Support of up to four differential lanes
  • Maximum 6,25Gbit/s lane speed
  • Up to 4 GByte trace buffer size, sufficient for up to 24 Giga CPU cycles

Off-chip Serial Trace via PowerTrace Serial (ETMv4)
  • 4 GByte trace memory
  • Universal module that is prelicensed for a trace protocol on delivery
  • Additional trace protocol licenses can be added
  • Up to 12.5 Gbit/s per channel
  • Maximum bandwidth of 100 GBit/s
  • Aurora-based trace protocols up to 8 RX lanes
  • PCIe 3.0-based trace protocol up to 8 RX/TX lanes
  • Reference-clock and bit-clock support
  • Fast trace upload to the host computer
  • Support for TRACE32 Streaming up to 180 MByte/s, compression allows higher data rates to be achieved
  • PODBUS Express interface to PowerDebug PRO
  • PODBUS and PODBUS Express interfaces to Logic Analyzer modules, e.g. PowerProbe, PowerIntegrator
  • Additional independent 17 channel logic analyzer (with included Standard Probe)


TRACE32 Debug Features

Multicore Debugging
  • Debugger for all cores of a multicore chip
  • Debugging of application cores, DSPs, accelerator cores and special-purpose cores
  • Debugging of more than 80 core architectures
  • Support for every multicore topology
  • Support for all multicore operation modes
  • Support for AMP and SMP systems
  • Single debug hardware can be licensed for all cores of a multicore chip

Logical Display of Peripherals
  • Display of onchip peripherals
  • User definable windows
  • Interactive window definition with softkey support
  • Pulldown menues for selection of choices
  • Additional description for each field

FLASH Programming (Memory-Mapped)
  • Optimum flash programming performance
  • Support for all file formats
  • Ready-to-run flash scripts
  • Ready-to-use flash programming algorithms
  • Dialog- or command-based programming as well as full scripting
  • Full awareness of sensitive data
  • Flash declaration via CFI
  • Easy handling of different flash types on a target
  • Software breakpoints in flash
  • Simple code patching in flash
  • Flash programming via boundary scan

NAND FLASH Programming
  • Generic and CPU-specific NAND FLASH controllers
  • Support all common NAND FLASH devices
  • Bad block treatment (skipped, reserved block area)
  • ECC generation

High-Level-Language Debugging
  • Supports multiple languages
  • Full support for C++
  • Integrated into TRACE32 environment
  • Supports most compilers and hosts
  • Same user interface on different hosts
  • High speed download
  • Debugs optimized code
  • Display of function nesting
  • Display of linked lists
  • Powerful expression evaluation

MMU Support
  • Full integrated support of processor's MMU
  • Display of processor MMU registers
  • Display of MMU table entries
  • Display of address translation table
  • 'Shadowing' MMU address translation inside debugger
  • Full virtual and physical access to target at any time
  • Debugger has optionally write access to write protected memory areas
  • Detection and decoding of software MMU tables built by operating systems
  • Support for several user space MMU tables side by side
  • TLB context tracking and git statistics via CTS

OS-aware Debugging
  • Real-time, non-intrusive display of RTOS system resources
  • Task stack coverage
  • Task related breakpoints
  • Task context display
  • SMP support
  • Task related performance measurement
  • Statistic evaluation and graphic display of task run times
  • Task related evaluation of function run times
  • PRACTICE functions for OS data
  • Easy access via RTOS specific pull-down menus
  • Support for all major RTOSes

Hypervisor-aware Debugging
  • Seamless debugging of the total system in stop-mode
  • Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
  • Machine ID allows the user to uniquely identify any virtual machine in the system
  • Machine ID provides full visibility of context of active and inactive virtual machines
  • OS-awareness can be loaded for each virtual machine

Sample-based Profiling
  • Long-time performance analysis for functions
  • Long-time performance analysis for tasks
  • Long-time analysis of the contents of a variable or memory location and more

Script Language PRACTICE
  • Structured Language
  • Menu Support
  • Command Logs
  • Custom Menues
  • Custom Toolbars and Buttons
  • Custom Dialog Windows
  • 64-Bit Arithmetic
  • Numeric, Logical and String Operators
  • Direct Access to System States


Details and Configurations

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The information presented is intended to give overview information only.
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Last generated/modified: 09-Oct-2019