Cortex-A/-R ARMv8 Debugger


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Adaptation
More TRACE32 Tools for ARMv8
TRACE32 Debug Features
Details and Configurations


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Cortex-A/-R  ARMv8  Debugger
  Highlights
Full support for all CoreSight components
Full architectural debug support

Support for 64-bit instruction set and 32-bit instruction sets ARM and THUMB
32-bit and 64-bit peripherals displayed on logical level
Support for 32-bit and 64-bit MMU formats
Auto-adaption of all display windows to AArch32/AArch64 mode

Ready-to-run FLASH programming scripts
Virtualization support
Bare metal and OS-aware debugging
Multicore debugging
Seamless debugging of big.LITTLE systems based on Cortex®-A57/Cortex®-A53, Cortex®-A72/Cortex®-A53, Cortex®-A73 or Cortex®-A35
AMP debugging with DSPs, GPUs and other accelerator cores
Support for 32-bit and 64-bit semi-hosting
Other TRACE32 tools for ARMv8: Debugging of Virtual Targets, On-chip trace support (ETB, ETF, ETR), Off-chip trace tools (ETMv4)


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List of Supported Compilers
List of Supported Target Operating Systems
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Ready-to-run bring-up scripts


[www.arm.com]  CoreSight On-chip Debug & Trace IP




 

Adaptation


Adaptation for ARM Debug Connector

Target Adaptation for MIPI-10/-20T/-20D/-34

 

More TRACE32 Tools for ARMv8


Debugging of Virtual Targets
  • Front-end to third-party virtual targets
  • Front-end to third-party core simulators
  • Front-end to third-party target servers
  • Front-end to TRACE32 Back-End
  • Same GUI as TRACE32 hardware debuggers
  • Debug features as provided by third-party software/TRACE32 Back-End
  • Trace features as provided by third-party software/TRACE32 Back-End
  • Windows, Linux and MacOSX
  • Reprise RLM floating licenses

On-Chip Trace (ETB, ETF, ETR)
  • Compatible to external ETM Trace
  • Readout through JTAG
  • No Speed Limit
  • Full Trace of Code and Data

Off-chip Parallel Trace (ETMv4)
  • Up to 4 GByte trace buffer
  • Target voltage 1.2 .. 3.3 V
  • 5 ns time stamp
  • Program and data trace
  • Performance analysis
  • Function and task run-time measurement
  • Code coverage
  • Support for Embedded Trace Macrocell (ETM), Program Trace Macrocell (PTM)
  • Support for Embedded Trace Buffer (ETB), Trace Memory Controller (TMC), Trace Port Interface Unit (TPIU)
  • Support for multiple trace sources in a single stream (CoreSight trace)

Off-chip Serial Trace via Serial Preprocessor (ETMv4)
  • Support of High-Speed Serial Trace Port (ETM-HSSTP, ARM specified)
  • Compatible to Xilinx Aurora protocol
  • Support of up to four differential lanes
  • Maximum 6,25Gbit/s lane speed
  • Up to 4 GByte trace buffer size, sufficient for up to 24 Giga CPU cycles

Off-chip Serial Trace via PowerTrace Serial (ETMv4)
  • 4 GByte trace memory
  • Universal module that is prelicensed for a trace protocol on delivery
  • Additional trace protocol licenses can be added
  • Up to 12.5 Gbit/s per channel
  • Maximum bandwidth of 100 GBit/s
  • Aurora-based trace protocols up to 8 RX lanes
  • PCIe 3.0-based trace protocol up to 8 RX/TX lanes
  • Reference-clock and bit-clock support
  • Fast trace upload to the host computer
  • Support for TRACE32 Streaming up to 180 MByte/s, compression allows higher data rates to be achieved
  • PODBUS Express interface to PowerDebug PRO
  • PODBUS and PODBUS Express interfaces to Logic Analyzer modules, e.g. PowerProbe, PowerIntegrator
  • Additional independent 17 channel logic analyzer (with included Standard Probe)

 

TRACE32 Debug Features


Multicore Debugging
  • Debugger for all cores of a multicore chip
  • Debugging of application cores, DSPs, accelerator cores and special-purpose cores
  • Debugging of more than 80 core architectures
  • Support for every multicore topology
  • Support for all multicore operation modes
  • Support for AMP and SMP systems
  • Single debug hardware can be licensed for all cores of a multicore chip

Logical Display of Peripherals
  • Display of onchip peripherals
  • User definable windows
  • Interactive window definition with softkey support
  • Pulldown menues for selection of choices
  • Additional description for each field

FLASH Programming (Memory-Mapped)
  • Optimum flash programming performance
  • Support for all file formats
  • Ready-to-run flash scripts
  • Ready-to-use flash programming algorithms
  • Dialog- or command-based programming as well as full scripting
  • Full awareness of sensitive data
  • Flash declaration via CFI
  • Easy handling of different flash types on a target
  • Software breakpoints in flash
  • Simple code patching in flash
  • Flash programming via boundary scan

FLASH Programming (Protocol-Based)
  • Optimum flash programming performance
  • Support for elf, Intel hex and S-record format
  • Ready-to-use flash programming scripts
  • Ready-to-use flash programming algorithms
  • Memory dump for displaying the flash content
  • Flash content can be easily copied and modified
  • Flash programming via boundary scan (SPI, eMMC, I2C)
  • Full programming access to spare area (NAND)
  • Bad block treatment (NAND)
  • ECC generation: Hamming, BCH, Reed-Solomon (NAND)

High-Level-Language Debugging
  • Supports multiple languages
  • Full support for C++
  • Integrated into TRACE32 environment
  • Supports most compilers and hosts
  • Same user interface on different hosts
  • High speed download
  • Debugs optimized code
  • Display of function nesting
  • Display of linked lists
  • Powerful expression evaluation

MMU Support
  • Full integrated support of processor's MMU
  • Display of processor MMU registers
  • Display of MMU table entries
  • Display of address translation table
  • 'Shadowing' MMU address translation inside debugger
  • Full virtual and physical access to target at any time
  • Debugger has optionally write access to write protected memory areas
  • Detection and decoding of software MMU tables built by operating systems
  • Support for several user space MMU tables side by side
  • TLB context tracking and git statistics via CTS

OS-aware Debugging
  • Real-time, non-intrusive display of RTOS system resources
  • Task stack coverage
  • Task related breakpoints
  • Task context display
  • SMP support
  • Task related performance measurement
  • Statistic evaluation and graphic display of task run times
  • Task related evaluation of function run times
  • PRACTICE functions for OS data
  • Easy access via RTOS specific pull-down menus
  • Support for all major RTOSes

Hypervisor-aware Debugging
  • Seamless debugging of the total system in stop-mode
  • Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
  • Machine ID allows the user to uniquely identify any virtual machine in the system
  • Machine ID provides full visibility of context of active and inactive virtual machines
  • OS-awareness can be loaded for each virtual machine

Sample-based Profiling
  • Long-time performance analysis for functions
  • Long-time performance analysis for tasks
  • Long-time analysis of the contents of a variable or memory location and more

Script Language PRACTICE
  • Structured Language
  • Menu Support
  • Command Logs
  • Custom Menues
  • Custom Toolbars and Buttons
  • Custom Dialog Windows
  • 64-Bit Arithmetic
  • Numeric, Logical and String Operators
  • Direct Access to System States

 

Details and Configurations






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The information presented is intended to give overview information only.
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Last generated/modified: 03-Dec-2019