TRACE32 is the state of the art debugger from Lauterbach. It comes with the universal user interface
PowerView running on your PC, MAC or Workstation and the smart debug probe
PowerDebug which connects via USB or Ethernet.
The PowerDebug connects via a DebugCable to you target chip via the
classic 5-Pin JTAG (IEEE 1149.1) or via the new 2-pin mode IEEE 1149.7
(often called cJTAG).
PowerDebug is a smart debug probe, which means that the debug driver software runs inside
the probe to react very fast on your CPU.
TRACE32 supports all DesignWare® ARC processors families from Synopsys:
- ARCv2™ architecture: ARC EM & ARC HS Families
- ARCompact™ architecture: ARC 600 & ARC 700 Families, ARCtangent-A5 Family
- ARCtangent™ 32-bit architecture: ARCtangent-A4 Family
The debugger supports all the powerful common TRACE32 features, such as on-chip breakpoints,
unlimited software breakpoints, online memory access,
snooping the program counter, RTOS support and multicore debugging.
Multicore debugging might be the strongest feature of TRACE32:
If you have a SoC containing several ARC DesignWare® cores or even other CPUs or DSPs you can
debug all your cores together with only one PowerDebug probel via a single JTAG port.
Especially for ARC DesignWare® TRACE32 supports:
- Full Actionpoints (Set breakpoints in Flash RAM or set Watchpoints on variables)
- Hostlink Library (Print messages from your target application directly to your debug GUI with a simple "printf")
- SmaRT (Use the small real time trace buffer of your ARC, to find out where an exception came from.)
Thanks to the universal user interface PowerView, Lauterbach provides the same look-and-feel for all processors. This gives you the chance to switch to DesignWare® ARC processors without further training for using the debugger.
PowerView runs on Windows, Linux, Mac and Solaris for both 32-bit and 64-bit machines. PowerView is fully scriptable, which means that any debugging sequence can be reproduced easily a thousand times.
Normal and Compact JTAG
- Normal JTAG IEEE 1149.1 (5-pin JTAG)
- Compact JTAG IEEE 1149.7 (2-pin JTAG)
- Variable Debug Clock Speed 10 kHz...50 MHz (≤ 1/2 core clock)
- High-Speed Download: 500 KByte/sec @ 50MHz JTAG clock
Full Memory Access
- Display/Read/Write of target memory while core is stopped or running
- Set/Delete Breakpoints while core is stopped or running
- Full access to auxiliary memory space
- Support for Code Overlays
Full Onchip Breakpoint support
- Program breakpoints
- Address read/write breakpoints (Watchpoints)
- Data breakpoints for memory writes
- Breakpoits on auxiliary registers
- Instruction data breakpoints for ARC700
- Breakpoits on core registers for ARCtagent-A4/A5
Hostlink Library Support
- Print messages from your target application directly to your TRACE32 GUI with a simple "printf"
- Open and save files on your host via your target application
- Supports Metaware Hostlink Library
- Support Lauterbach Hostlink Library for GNU and Metaware compiler
- Debugging of several CPUs via just a single debug port
- Homegenous multicore debugging with other ARC cores
- Heterogeneous multicore debugging with ARC® and ARM®, MIPS® or ATOM™ cores
- Multicore debugging in JTAG Daisy Chain or MADI
- Other multicore configurations on request
Screenshot of TRACE32® PowerView for ARC
- Based on Nexus message protocol (small, medium or full)
- Program, data and register trace
- Trace protocol may include timestamps or cycle count
- Multicore tracing
- Trace filter allow to reduce the generation of trace messages
- ARC-only trace or integrated into an Arm CoreSight trace infrastructure
- Onchip trace, parallel Nexus trace port, CoreSight TPIU, Arm HSSTP
IDE - Integrated Development Environment