PowerProbe - Logic and Protocol Analyzer


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Picture
  Highlights
Timing Analyzer up to 400 MHz
State Analyzer up to 100 MHz
64 Input Channels
Transient Recording
Time Correlation with RISC Trace
Clock Qualifier for State Clock
Mixed State and Timing Mode
4 State Clock Inputs
Optional FPGA Onchip Trace
Optional Pattern Generator
Protocol Support for CAN, USB, etc.
 
  Introduction
The Timing/State Analyzer Module is special designed for microprocessor applications. It can work separately or in conjunction with all ICD modules. The high-speed transient recording allows very long record time when tracing peripheral lines in a microcontroller application.


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Logic Analyzer




Basics

    The Timing/State Analyzer is specially designed for microprocessor applications. The modul supports timing and state analysis up to 400 MHz.

Input Channels

    5 operating modes:

  • 64 channels timing mode 100 MHz
  • 32 channels timing mode 200 MHz
  • 16 channels timing mode 400 MHz (256K Version)
  • 32 channels state mode 100 MHz
  • 32 channels timing muxed mode for SOC-CON + 32 channels timing mode 100 MHz
  • 32 channels timing muxed mode for SOC-CON + 16 channels timing mode 200 MHz
  • 32 channels timing muxed mode for SOC-CON + 8 channels timing mode 400 MHz
  • State or timing mode for every channel selectable
  • 4 state clock signals, sampling on rising or falling edge

Input Signals

  • Selectable threshold level for groups of 16 lines
    • 1.0V for low voltage target systems (1.5 .. 2.5 V)
    • 1.4V for normal voltage target systems (CMOS + TTL 2.5 .. 5 V)
  • 100 KOhm/10 pF 0..10 V with probe compensation

Transient Recording over required Time

    The recording depth is governed by the number of transitions on the transient sensitive inputs.




High Memory Depth

  • 128K (256K) timing transients or state edges

Transient sensitivity can be activated independently for each channel

Time Stamp Unit with 10ns Resolution

Time Correlation with all other Clocks and Analyzers of the System

  • Timing Analyzer can track to State Analyzer or PowerTrace
  • Time Correlation within 10 ns


4 Clock Qualifier Inputs in Synchronous Mode

    The clock qualifier inputs can be synchronised with the input clock

Master-Slave Operation in Conjunction with other Analyzers

Simple Trigger

  • 1 Complex comparator with HIGH, LOW, RISING, FALLING or DON'T CARE for each input
  • More than one clock edges can be selected for trigger condition



  • Direct setting in timing display window

Trigger Filter

  • Up to 2.5 us

Asynchronous Trigger



  • 8 Input Lines
  • Clock and Data Comparator
  • Synchr. Trigger Register
  • Pulse Width Triggering
  • Glitch Trigger

Trigger Output for Scope etc.

Triggering through Bus Trigger Lines

Programmable Trigger and Pretrigger Delay 0 to 1000% of Records

Triggering of other System Units

Trigger Output for Scope etc.

Various output formats

  • Binary
  • VHDL
  • Verilog

Pulse Generator

  • 10 ns .. 40 s pulse width
  • 20ns .. 40 s period
  • High, low or symetric pulse
  • Single trigger
  • Trigger by complex trigger unit
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Protocol Support


Protocol Analysis



  • CAN Support
  • FlexRay Support
  • LIN Support
  • SPI Support
  • USB Support
  • I2C Support
  • JTAG Support
  • ASYNC Support
  • PCI Support
  • DRAM Support
  • User Specific Protocols


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Disassembler Support


  • Many disassemblers can be selected for bus trace operations
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Option SOC-CON (System-On-Chip)



    The SOC-CON is a scalable connector for tracing FPGAs and ASICs with a limited number of signal lines. Up to 1024 internal signals can be traced at the same time.



    Adaption for Excalibur (ALTERA)
    • JTAG Debugger for ARM9
    • ETM Trace for Flow Trace
    • SOC-CON for OnChip Trace

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Option Complex Trigger (256K Version)


Trigger Sequencer

  • Free programmable trigger sequencer with 4 levels




Complex trigger controls pattern generator, etc.




Trigger Comparators

  • 8 Trigger comparators with 64 Bit each with HIGH, LOW, DON'T CARE, RANGE and EDGE detection

4 Trigger Levels

  • 4 global event, no death time

3 Retriggerable 45 Bit Counters in Trigger System

  • Time window definition
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Option Pattern Generator (256K Version)


Pattern Display

  • List Mode
  • Timing Mode

9 Channels

10ns Cycle Time

External/Internal Clock

  • 100 MHz internal
  • 0..50 MHz external
  • Rising/falling edge
  • Single step

Clock Qualifier

  • High
  • Low
  • Don't care

Trigger Input

  • BUS
  • External
  • Trigger mode
    • High
    • Low
    • Rising
    • Falling

Clock Enable Input

Trigger Output to BUS

Retrigger Function

  • Wait for trigger
  • Restart

Pattern Definition



  • Standby
  • Set
  • Repeat
  • (block)
  • Delay
  • Wait
  • Restart
  • Stop











Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 1-Aug-2016