PowerIntegrator - Logic and Bus Analyzer


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Picture
  Highlights
Timing Analyzer with 500 MHz on all Channels
State Analyzer up to 200 MHz DDR
204 Input Channels
Transient Recording
Time Correlation with other Tracetools
Clock Qualifier for State Clock
Mixed State and Timing Mode
4 Clock Inputs
MICTOR and Standard Probes (single ended)
MICTOR differential Probes
Analog Voltage and Current Probe
3G/DigRF Protocol Support
 
  Introduction
The PowerIntegrator module replaces much more expensive logic analyzer systems used for microprocessor system integration. High-speed logic analysis is now possible on every workplace integrated in the debugger software.


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Logic Analyzer





Debugger with Target for ARM9 and 204-Channel Logic-Analyzer




















Single MICTOR Probe

Basics

    The PowerIntegrator Logic Analyzer is specially designed for microprocessor system integrations. The modul supports timing and state analysis up to 500 MHz.

Fast Upload

  • 500 KBytes/sec

Time Stamp Unit with 4ns Resolution

Time Correlation with all other Clocks and Analyzers of the System

Master-Slave Operation in Conjunction with other Analyzers

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Timing Analyzer


Input Channels

   2 timing operating modes:
  • 102 channels timing mode 500 MHz 1024K Records
  • 204 channels timing mode 250 MHz 512K Transients

Transient Recording over required Time

High Memory Depth

  • 256K low speed timing transients or state edges

Transient sensitivity can be activated independently for each channel

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State Analyzer


Input Channels

   4 state operating modes:
  • 204 channels state mode 200 MHz 512K Trace (clock A or B)
  • 102 channels state mode 200 MHz 512K Trace (clock A or B) Double Data Rate
  • 102 channels state mode 200 MHz 512K Trace (clock A or B) and
  • 102 channels state mode 200 MHz 512K Trace (clock J or K)
  • sampling on rising or falling clock edge,

Direct Integration in Debugger Software

Complex Bus Oriented Triggering

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Trigger


Simple Trigger

  • 1 Complex comparator with HIGH, LOW, RISING, FALLING or DON'T CARE for each input
  • More than one clock edges can be selected for trigger condition
  • Direct setting in timing display window

Complex Trigger

  • Free programmable trigger sequencer with 4 levels

Trigger Events

  • 2 Trigger comparators with 64 Bit each on every trigger level with HIGH, LOW, DON'T CARE and RANGE
  • 8 Address Selectors with 32-Bit Range

4 Trigger Levels

  • 4 global event, no death time

Trigger Filter

  • Up to 2.5 us

3 Retriggerable 44 Bit Counters in Trigger System

  • Time window definition

Trigger Output for Scope etc.

Triggering through Bus Trigger Lines

Programmable Trigger and Pretrigger Delay 0 to 1000% of Records

Triggering of other System Units

Trigger Output for Scope etc.

Trigger Input

  • BUS
  • External
  • Trigger mode
    • High
    • Low
    • Rising
    • Falling
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Formats


Various storage formats

  • Binary
  • VHDL
  • Verilog
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Additional Software Features


Protocol Analysis
  • CAN Support
  • FlexRay Support
  • LIN Support
  • SPI Support
  • USB Support
  • I2C Support
  • JTAG Support
  • ASYNC Support
  • PCI Support
  • DRAM Support
  • User Specific Protocols

Energy Profiling
  • Realtime measurement of 3 current and 4 voltage lines
  • Realtime trigger on current, voltage and power
  • Time correlation with other TRACE32 tracetools
  • Energy statistics on function and task level
  • Fully integrated in the TRACE32 user interface

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Disassembler Support


  • Many disassemblers can be selected for bus trace operations
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Probes


MICTOR Probe


  • 34 channel MICTOR probe (32 Data, 2 Clocks)
  • Selectable threshold level for groups of 17 lines (16 Data, 1 Clock)
  • 0.1..5.0 V
  • 50 KOhm/4 pF 0..5 V with probe compensation
Signal

Pin

 Pin

Signal

    
N/C12N/C
GND34N/C
CLK056CLK1
D1578D31
D14910D30
D131112D29
D121314D28
D111516D27
D101718D26
D91920D25
D82122D24
D72324D23
D62526D22
D52728D21
D42930D20
D33132D19
D23334D18
D13536D17
D03738D16
    
N/C pins must be left open, Connect pin 39,40,41,42,43 to GND





MICTOR Differential Clock Probe


  • 33 channel MICTOR probe (32 Data, 1 Clock Pair)
  • Selectable threshold level for groups of 16 lines
  • 0.1..5.0 V
  • 50 KOhm/4 pF 0..5 V with probe compensation
Signal

Pin

 Pin

Signal

    
N/C12N/C
GND34N/C
CLK+56CLK-
D1578D31
D14910D30
D131112D29
D121314D28
D111516D27
D101718D26
D91920D25
D82122D24
D72324D23
D62526D22
D52728D21
D42930D20
D33132D19
D23334D18
D13536D17
D03738D16
    
N/C pins must be left open, Connect pin 39,40,41,42,43 to GND





MICTOR Differential Probe


  • 17 channel MICTOR probe (16 Data Pairs, 1 Clock Pair)
  • 0.1..5.0 V
  • 50 KOhm/4 pF 0..5 V with probe compensation
Signal

Pin

 Pin

Signal

    
N/C12N/C
GND34N/C
CLK+56CLK-
D15+78D15-
D14+910D14-
D13+1112D13-
D12+1314D12-
D11+1516D11-
D10+1718D10-
D9+1920D9-
D8+2122D8-
D7+2324D7-
D6+2526D6-
D5+2728D5-
D4+2930D4-
D3+3132D3-
D2+3334D2-
D1+3536D1-
D0+3738D0-
    
N/C pins must be left open, Connect pin 39,40,41,42,43 to GND





SAMTEC Probe


  • 34 channel SAMTEC probe (32 Data, 2 Clocks)
  • Selectable threshold level for groups of 17 lines (16 Data, 1 Clock)
  • 0.1..5.0 V
  • 50 KOhm/4 pF 0..5 V with probe compensation
Signal

Pin

 Pin

Signal

    
GND12GND
N/C34N/C
GND56GND
D1678D0
GND910GND
D171112D1
GND1314GND
D181516D2
GND1718GND
D191920D3
GND2122GND
D202324D4
GND2526GND
D212728D5
GND2930GND
D223132D6
GND3334GND
D233536D7
GND3738GND
D243940D8
GND4142GND
D254344D9
GND4546GND
D264748D10
GND4950GND
D275152D11
GND5354GND
D285556D12
GND5758GND
D295960D13
GND6162GND
D306364D14
GND6566GND
D316768D15
GND6970GND
N/C7172N/C
GND7374GND
N/C7576N/C
GND7778GND
CLK17980CLK0
GND8182GND
N/C8384N/C
GND8586GND
N/C8788N/C
GND8990GND
N/C9192N/C
GND9394GND
GND9596GND
N/C9798N/C
N/C99100N/C
    
N/C pins must be left open





SAMTEC Differential Clock Probe


  • 33 channel SAMTEC probe (32 Data, 1 Clock Pair)
  • Selectable threshold level for groups of 16 lines
  • 0.1..5.0 V
  • 50 KOhm/4 pF 0..5 V with probe compensation
Signal

Pin

 Pin

Signal

    
GND12GND
N/C34N/C
GND56GND
D1678D0
GND910GND
D171112D1
GND1314GND
D181516D2
GND1718GND
D191920D3
GND2122GND
D202324D4
GND2526GND
D212728D5
GND2930GND
D223132D6
GND3334GND
D233536D7
GND3738GND
D243940D8
GND4142GND
D254344D9
GND4546GND
D264748D10
GND4950GND
D275152D11
GND5354GND
D285556D12
GND5758GND
D295960D13
GND6162GND
D306364D14
GND6566GND
D316768D15
GND6970GND
N/C7172N/C
GND7374GND
N/C7576N/C
GND7778GND
CLK-7980CLK+
GND8182GND
N/C8384N/C
GND8586GND
N/C8788N/C
GND8990GND
N/C9192N/C
GND9394GND
GND9596GND
N/C9798N/C
N/C99100N/C
    
N/C pins must be left open





Standard Probe


  • 17 channels
  • Selectable threshold level (16 Data, 1 Clock)
  • 0.1..5.0 V
  • 50 KOhm/4 pF 0..5 V with probe compensation


Signal

Pin

 Pin

Signal

    
N/C12N/C
CLK34D15
D1456D13
D1278D11
D10910D9
D81112D7
D61314D5
D41516D3
D21718D1
D01920GND
    



Analog Probe


  • 4 Voltage Channels 12 bit 0..5 V, 1 MOhm
  • 3 Current Channels 5% Accuracy, external Shunt
  • 625 KSampes/sec sampling rate

Signal

Pin

 Pin

Signal

    
I2-12GND
I2+34GND
I1-56GND
I1+78GND
I0-910GND
I0+1112GND
V31314GND
V21516GND
V11718GND
V01920GND
    



USB2 Probe


  • Recording of USB2 and USB1.x protocol
  • Filter, trigger and display on PID protcol level



DigRF ProbeSet


  • probe set (3 pieces) for 3G/DigRF protocol
  • differential RX
  • differential TX
  • single ended SysClkEna
  • single ended ANY (for free use)
Signal

Pin

 Pin

Signal

    
RX+12GND
N/C34N/C
RX-56GND
    
Signal

Pin

 Pin

Signal

    
TX+12GND
N/C34N/C
TX-56GND
    
Signal

Pin

 Pin

Signal

    
CLKEN12GND
N/C34N/C
SYSCLK56GND
    



DRAM Adapter


  • 184 Pin DIMM
  • 144 Pin SO_SDRAM
  • 200 Pin SO_DDR
  • 200 Pin SO_DDR2

Adaptions for PowerIntegrator



  • Definitions for Evaluation Boards
  • Setup Scripts





Board Adapter


  • Adapters for Tektronix and Agilent Adaptions




Copyright © 2014 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice.
Last generated/modified: 14-Apr-2014