Unified debug interface to both real hardware and software simulations
Today, SoC design flows span several levels of abstraction, ranging from high level simulations to the final integrated hardware. Throughout this design, various off-the-shelf components of intellectual property (IP) are assembled in order to achieve high quality designs in short time. The Open SoC Design Platform for Reuse and Integration of IPs (SPRINT) Project has taken the challenge to develop a standards-based platform supporting the creation of interoperable and reusable IP as well as their efficient integration into high class SoCs. The SPRINT consortium consists of numerous companies and research facilities from the IP business, including both providers and users.
Within the scope of this project, ARM, Infineon Technologies, Lauterbach, NXP Semiconductors, STMicroelectronics and TIMA Laboratory jointly created the MCD API. It was designed to provide debug tools with a unified debug interface to both real hardware and software simulations. This allows engineers to start the application development early in the SoC platform design flow without having to switch to other debug tools during the transition from virtual prototypes to real hardware. Furthermore, the MCD API addresses multi-core debugging which is inevitable due to the complexity of today's SoC designs. Experiments within the SPRINT project have proven the feasibility and applicability of the interface.
A powerful but simple C-interface
The MCD API provides the necessary means in order to perform efficient application debugging for multi-core SoCs and comes with a set of sub-APIs offering the following features:
Connection/instantiation and configuration of debug servers in order to connect debug tools to multi-core systems; multiple cores of a system can be connected to a tool simultaneously.
Target System Description
Retrieving information about the connected system through API function calls and IP-XACT descriptions (as specified by the SPIRIT consortium); enables retargetability of the debug tool and additional debug and analysis features.
Target Run Control
Run control designed for multi-core systems; the reaction of a system's processing units to these calls can be configured core by core.
Generic trigger interface; offers predefined trigger types (e.g. for breakpoints) and allows customized ones; cross-triggering is possible via trigger buses.
Generic trace interface; offers predefined trace sources and allows customized ones.
Memory and Register Accesses
Unified memory and register access mechanism using transaction lists.