Emulators & Virtual Targets
Start Development Even Before Chips are Available in Silicon
Shift-left testing is an approach to software testing and system testing in which testing is performed earlier in the lifecycle, i.e., moved left on the project timeline. TRACE32® supports this approach by supporting not only real chips in silicon, but also virtual targets and emulators from various partner suppliers, on which software development is already possible when no real chips in silicon are available.
Supported Emulators
Thanks to Lauterbach’s Generic Transactor Library (GTL) API you can debug all market-leading emulators to access your pre-silicon designs in early development stages.
Synopsys HAPS-200 is a high performance and scalable pre-silicon prototyping system and iis used in pre-silicon software development, as well as at-speed interface validation.
.jpg)
Cadence Palladium emulation platforms provide early hardware/software co-verification and debug and in-circuit emulation early in the design cycle when the RTL is still changing.
Cadence Protium prototyping platforms provide a pre-silicon platform for early software development, SoC verification, system validation, and hardware regressions.
Veloce CS is a leading hardware software and system validation platform meeting the demands of complex chips, software, and systems.
Synopsys ZeBu-200 is the ideal platform to execute complex and long running workloads needed for power, performance analysis and software/hardware validation.
Supported Simulators & Virtual Targets
Start your software development early by connecting TRACE32® to virtual targets and simulators running on Remote-PCs as well in the cloud. TRACE32® is supporting by far the most virtual targets and 3rd party simulators in the tool industry.
The Synopsys ARC® nSIM Instruction Set Simulator provides an instruction accurate processor model for the ARC processor families enabling an early start.
Architecture Envelope Models (AEMs) are generic Fixed Virtual Platforms (FVP) suitable for early Arm Architecture exploration.
.jpg)
Arm Virtual Hardware powered by Corellium uses virtualization technology to provide cloud-native, Arm-based virtual devices that run at or above the speed of actual silicon.
Synopsys’ ASIP Designer™ is a tool suite that brings Application-Specific Instruction-Set Processors (ASIP) design within easy reach of every SoC team.
Fast Models are accurate, flexible programmer's view models of Arm IP, allowing to develop software such as drivers, firmware, OS and applications.
Fixed Virtual Platforms (FVP) are complete simulations of an Arm system, including processor, memory and peripherals.
High-performance, re-targetable instruction set simulator which can be effortlessly re-targeted to different processor architectures.
.jpg)
QEMU (Quick Emulator) is a free virtualization software that emulates the entire hardware of a computer and dynamically translates the processor instructions.
The Hexagon processor instruction set simulator simulates the execution of Hexagon programs and supports interactive debugging by serving as a simulation engine.
.jpg)
SIM-V is a high-speed RISC-V system simulator designed for scalable software development and testing, enabling early validation even before hardware prototypes are available.
.jpg)
Virtualizer Development Kits (VDKs) empower developers to build, test, and validate software without physical hardware. Customers can create their own VDKs to support their supply chain.
Fast virtualization of your SoC, MCU, ECU, or electronics system. Use TRACE32 to debug unmodified binaries in a virtual environment. Accelerate CI/CD, testing, and analysis without relying on hardware.
Qualcomm branded products are products of Qualcomm Technologies, Inc. and/or its subsidiaries.
QEMU logo by Benoît Canet, licensed under CC BY 3.0
Connect any of your Virtual Targets
Depending on the microarchitecture(s) used, there are many different ways to connect debug and trace tools to virtual targets. Our TRACE32®️ tools provide broad support for architectures and interfaces.
| Interface | Supported Architectures |
| ARCINT | Synopsys ARC |
| CADI | Arm (Cortex-A, R, M, X) |
| GDB | Arm (Cortex-A, R, M, X, Neoverse), TriCore, PowerPC, Intel x86/x64, UBI32, i8051, MIPS, STRED, C6000, NIOS, TPU, 68K |
| GDI | TriCore, C166, Arm (only Cortex-M v7), PowerPC, V850, C5000, Hexagon, MIPS |
| GTL | RTL Emulator, find more details here |
| Iris | Arm (Cortex-A, R, M, X) |
| MCD | Arm (Cortex-A, R, M, X), ARC, C7000, Hexagon, RISC-V, TriCore, Intel x86/x64, GTM, UBI32, V850/RH850, PowerPC, CEVA-Teak/CEVA-TeakLite, Tensiica Xtensa, i8051, CEVA-X, VSPA, IPU |
| MDI | MIPS, ZSP |
| TSI | C2000, C5000, C6000 |