- Multicore tracing via on-chip trace for Emulation Devices
- Medium speed multicore off-chip tracing via DAP interface with up to 128 MB trace memory, if necessary long-term trace by streaming to the host
- Multicore off-chip tracing via high-speed serial AGBT interface with up to 4GB trace memory, if necessary long-term trace by streaming to the host
- Performance profiling and qualification, e.g. Cache analysis, Code coverge
TRACE32 allows multicore debugging for up to three TriCore cores and all auxiliary controllers.
- The cores can be started and stopped synchronously
- The state of all cores can be displayed side by side
- All cores can be controlled by a single script
Debug Port Sharing with 3rd Party Tools
Some third-party tools access the target using the JTAG or DAP debug port as well.
Using such a tool simultaneously with TRACE32 tool requires sharing the debug port between both tools. The
following port sharing technologies are supported:
Port Sharing by Using the XCP Protocol
Hardware-assisted Port Sharing
- Supports sharing the JTAG or DAP debug port with 3rd party tools, e.g. ETAS ETK, dSpace GSI and Vector VX1000
- Debug port is switched automatically between 3rd party tool and TRACE32 tool
- Usage of on-chip resources can be restricted to allow concurrent use of 3rd party tool
Benchmark counters are on-chip counters that count specific hardware events. A typical example are counters for cache hits and misses allowing the calculation of the corresponding performance metrics.
- Configuration and observation of
- On-chip performance counters of cores, counting, e.g., executed instructions, cache hits and cache misses, CPU stalls, ...
- MCDS event counters on Emulation Devices, supporting, e.g., user events, access counters for various memories, ...
- Periodically read-out of counters during runtime (Snooper)
- Start and stop of counters using on-chip triggers to allow fine-grained investigation of single code part
Debug and Trace Through Reset
Microcontroller applications are often secured by an internal and/or external watchdog or internal surveillance. In case of any unrecoverable error these systems reset the microcontroller in order to bring it back into a known and safe state. When such a reset occurs during development, the engineers want to know why this error happens, and often how post-error handling after reboot behaves.
Debug and trace through reset are supported by the Bi-directional and Automotive debug cables.
- The debugger is able to detect the reset event and to reconnect to the device after the reset has been released again. The user can configure the debugger′s behaviour in this case: halt target at reset vector or resume application. The debug resources, e.g. on-chip breakpoints, trace and trigger configuration are reprogrammed.
- In case trace recording was enabled the information of what happened prior to the reset is contained in the trace and can be displayed even after the reset. If the debugger is programmed to resume program execution the trace will continue recording (not possible for on-chip trace in case of a hard reset, e.g. PORST).
MCDS Trace Message Generation and Trigger
The MCDS module of the Emulation Devices generates information on the instruction execution and data accesses of up to two cores in parallel as well as transfers on the on-chip buses.
- MCDS is used for generating unfiltered and filtered trace messages
- Support for tracing of up to two TriCore cores or an auxiliary core (GTM or PCP):
- Program flow or sync trace (generating trace messages on branches or on every MCDS clock cylce)
- Data trace: write address and data, read address (device dependent)
- Ownership information, e.g. PCP channel ID (device dependent)
- Support for tracing the processor bus (LMB, SRI) and the peripheral bus (SPB, RPB)
- Data trace: read/write address and data, ownership information, e.g. bus master, DMA channel, supervisor mode
- SRI trace allows tracing of data transfers to up to two SRI bus slaves in parallel
- Pre-defined filter setups, e.g. for OS-aware trace
- Trace through reset support
The on-chip trace stores the trace information generated by the MCDS into a trace buffer of the Emulation Device. With its configurable size of up to 1 MB it is perfect for detailed troubleshooting and in-field testing. Filters and triggers allow an effective usage of the trace memory.
- Up to 1 MB of configurable on-chip trace memory
- Trigger and filter programming for an efficient use of the trace buffer
- Configurable on-chip memory allows a concurrent usage of the on-chip trace with third-party usage, e.g. calibration tools or the user application
- Fully supported by standard debugger, no additional hardware required
When information about program execution and data access by cores and/or buses are provided at external pins this information can be stored by the trace tool. It allows detailed qualification and analysis with its up to 4GB trace buffer and the possibility of streaming to the host storage.
While many TriCore AUDO devices have a parallel trace port most of the TriCore AURIX Emulation Devices support the AGBT high-speed serial trace using the Aurora protocol.
- Robust trace recording using Aurora
- Up to 6.25 GBit/s per lane
- Up to 4 lanes
- Up to 8 GByte trace memory
- Streaming to host storage
- Delay counter
- Fast search and download
- Code Coverage
- Performance Analysis
- 4 GByte trace memory
- Universal module that is prelicensed for a trace protocol on delivery
- Additional trace protocol licenses can be added
- Up to 12.5 Gbit/s per lane
- Maximum bandwidth of 100 GBit/s
- Aurora-based trace protocols up to 8 RX lanes
- PCIe 3.0-based trace protocol up to 8 RX/TX lanes
- Reference-clock and bit-clock support
- Fast trace upload to the host computer
- Support for TRACE32 Streaming up to 400 MByte/s
- Additional independent 17 channel logic analyzer (with included Standard Probe)
- Debug cable and 512 MByte of trace memory
- Whisker cable with 26-pin automotive connector
- Same debug features as the TRACE32 Debug Cables for TriCore
- 512 MB of trace memory for DAP Streaming
- DAP Streaming with up to 30 MByte/s
- DAP streaming requires a DAP mode, for performance reasons, we recommend DAPWide at 160 MHz
- DAP Streaming for filtered tracing, GTM tracing and Compact Function Trace
- TRACE32 Streaming for long-time recording
The instruction and data caches on TriCore devices can be accessed with TRACE32.
- For each cache line the valid bit and LRU information is available, data caches additionally provide the dirty bit
- Cached memory regions can be highlighted in the respective windows, e.g. the Data.dump or the List.auto window.
- When debugging, TRACE32 can be configured to transparently display variable values from the cache (i.e. from the CPUs point of view).
- In-depth cache analysis is provided with the CACHE. command group.
The Standby Controller (SCR) is an 8-bit microcontroller that can continue to run during the standby mode. It is based on the XC800 core that is compatible with the industry standard 8051 processor. It includes an On-chip Debug Support (OCDS) unit for software development and debugging of XC800-based systems via single pin DAP interface. For the moment it is implemented on the TC2X cores.
- Fast hll and assembler debugging
- Interface to all standard compilers
- Full support for all on-chip breakpoints
- Unlimited number of software breakpoints
- Display of internal and external peripherals at a logical level
- Flash programming
- Interface to all hosts
- Batch processing by script language PRACTICE
The debugger for the General Timer Modul (GTM) is a free add-on to the debugger for AURIX family and will be accessed in a separate instance of the TRACE32 software.
- Full debug support of GTM
- GTM debug support included in the TriCore debug license
- GTM trace - MCS (Multi Channel Sequencer)
- GTM trace - ARU (Advanced Routing Unit)
- GTM trace - I/O channels
- GTM trace support included in the MCDS trace license
The debugger for the Peripheral Control Processor (PCP) is a free add-on to the debugger for AUDO family and will be accessed in a separate instance of the TRACE32 software.
- Full HLL support
- Disassembler for PCP Instructions
- Supports ELF/DWARF format
- Batch Processing
- Debug Access via JTAG and DAP
- 3.3 Volt Support
- Unlimited Software Breakpoints on Code
- Emulation Device support (additional triggers via MCDS)
- PCP debugging comes for free with TriCore OCDS Debugger
- PCP tracing
- PCP tracing comes for free with Preprocessor TriCore OCDS-L2
Flyer "Debug & Trace for TriCore"
A variety of adaptors and converters are available for the connection between debug cables and targets.
Adaptation for Automotive Debug Cable
- Supports debugging using DAP and JTAG
- Half Size (1.27 mm pitch) target connector with 10-/20- and 26-pins (AUTO10/AUTO20/AUTO26)
- Many adaptators available including ECU14 and 16-pin OCDS connector
Adaptation for Standard TriCore Debug Cable
- Supports debugging using DAP and JTAG
- 16-pin OCDS target connector
- Many adaptators available including ECU14 and 10-pin DAP
IDE - Integrated Development Environment