TriCore Debugger

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TriCore-specific Debug Features
Generic TRACE32 Debug Features

TriCore Debugger
Multicore debugging
Debugging of TriCore and all auxiliary controllers
TC4xx: up to 6 TriCore, CSRM (TriCore), SCR (XC800), PPU (ARC), GTM
TC2xx/3xx: up to 6 TriCore, HSM (Cortex-M), SCR (XC800), GTM
AUDO: TriCore, PCP

Debug access via JTAG and DAP
AUTOSAR-aware debugging
Hypervisor-aware debugging for TC4xx

Debug for Synopsys Virtualizer Development Kit (VDK)
Debug via XCP
Tool Qualification Support Kit (TQSK) for TRACE32 Instruction Set Simulator TriCore
For more than 20 years Lauterbach TRACE32® tools have been supporting the Infineon TriCore™ microcontrollers, the latest AURIX™ multicore architectures as well as the well-proven single core AUDO devices.

Link Support
Technical Support
TRACE32 for Tricore: An Overview



Adaptation for Automotive Debug Connector

Adaptation for TriCore Debugger Standard

A variety of converters is available to connect the debug cable to the target.

   Article "Application Note Debug Cable TriCore"



Debug Features

Debug Solutions

Trace TriCore

TriCore™ AURIX™ Trace
  • Based on MCDS trace protocol
  • Multicore tracing of up to 6 TriCores, PPU (ARC), GTM and PCP
  • Instruction trace
  • Data trace
  • Trace of transfers via on-chip buses and interconnects
  • Tool and chip timestamps
  • On-chip trace for product- and emulation devices
  • High-speed serial trace for Emulation Devices (AGBT/SGBT)
  • DAP streaming for CombiProbe
  • Comprehensive profiling of functions, tasks, data etc.
  • AUTOSAR-aware profiling
  • Code coverage measurement for functional safety
  • Trace for Synopsys Virtualizer Development Kit (VDK)
  • Trace via XCP
  • Tool Qualification Support Kit (TQSK) for TRACE32 Instruction Set Simulator TriCore


TriCore-specific Debug Features

Multicore Debugging

TRACE32 allows multicore debugging for all TriCore cores and all auxiliary controllers.
  • The cores can be started and stopped synchronously
  • The state of all cores can be displayed side by side
  • All cores can be controlled by a single script

Debug Port Sharing with 3rd Party Tools

Some third-party tools access the target using the JTAG or DAP debug port as well. Using such a tool simultaneously with TRACE32 tool requires sharing the debug port between both tools. The following port sharing technologies are supported:

Port Sharing Using the XCP Protocol

For details refer to Debugging via XCP

Hardware-assisted Port Sharing
  • Supports sharing the JTAG or DAP debug port with 3rd party tools, e.g. ETAS ETK, dSpace GSI and Vector VX1000
  • Debug port is switched automatically between 3rd party tool and TRACE32 tool
  • Usage of on-chip resources can be restricted to allow concurrent use of 3rd party tool

Benchmark Counters

Benchmark counters are on-chip counters that count specific hardware events. A typical example are counters for cache hits and misses allowing the calculation of the corresponding performance metrics.
  • Configuration and observation of
    • On-chip performance counters of cores, counting, e.g., executed instructions, cache hits and cache misses, CPU stalls, ...
    • OTGS event counters
    • MCDS event counters on Emulation Devices, supporting, e.g., user events, access counters for various memories, ...
  • Periodically read-out of counters during runtime (SNOOPer)
  • Start and stop of counters using on-chip triggers to allow fine-grained investigation of single code part

Debug Through Reset

Microcontroller applications are often secured by an internal and/or external watchdog or internal surveillance. In case of any unrecoverable error these systems reset the microcontroller in order to bring it back into a known and safe state. When such a reset occurs during development, the engineers want to know why this error happens, and often how post-error handling after reboot behaves. The debugger is able to detect the reset event and to reconnect to the device after the reset has been released again. The user can configure the debugger′s behaviour in this case: halt target at reset vector or resume application. The debug resources, e.g. on-chip breakpoints, trace and trigger configuration are reprogrammed.

Cache Debugging

The instruction and data caches on TriCore devices can be accessed with TRACE32.
  • Cached memory regions can be highlighted in the respective windows, e.g. the Data.dump or the window.
  • When debugging, TRACE32 can be configured to transparently display variable values from the cache (i.e. from the CPUs point of view).
  • In-depth cache analysis is provided with the CACHE command group. For example, valid bit, dirty bit and LRU information can be displayed for each line of the data cache.


Generic TRACE32 Debug Features

Multicore Debugging
  • Debugger for all cores of a multicore chip / multiprocessor system
  • Debugging of high-performance and real-time cores, DSPs, accelerator and special-purpose cores
  • Support for every multicore topology
  • Support for all multicore operation modes
  • Support for AMP, iAMP and SMP systems
  • Single debug hardware can be licensed for all cores of a multicore chip / multiprocessor system

OS-aware Debugging
  • Real-time, non-intrusive display of RTOS system resources
  • Task stack coverage
  • Task related breakpoints
  • Task context display
  • SMP support
  • Task related performance measurement
  • Statistic evaluation and graphic display of task run times
  • Task related evaluation of function run times
  • PRACTICE functions for OS data
  • Easy access via RTOS specific pull-down menus
  • Support for all major RTOSes

AUTOSAR-Aware Debugging: Classic Platform
  • ORTI and ARTI compliant
  • Single-core and SMP operating systems
  • Support for all standard AUTOSAR providers such as Elektrobit, ETAS, Vector
  • Concurrent debugging of multiple AUTOSAR Classic platforms

Hypervisor-Aware Debugging for TC4xx
  • Seamless debugging of the total system in stop-mode
  • Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
  • Hypervisor-aware debugging for high-performance cores (MMU) such as Arm Cortex, PowerArchitecture and Intel x64
  • Hypervisor-aware debugging for selected real-time cores (MPU) such as Arm Cortex-R52/-R82, RH850 (G4MH4 core and later) and TriCore TC4x
  • Machine ID allows the user to uniquely identify any virtual machine in the system
  • Machine ID provides full visibility of context of active and inactive virtual machines
  • OS-awareness can be loaded for each virtual machine

Script Language PRACTICE
  • Structured Language
  • Menu Support
  • Command Logs
  • Custom Menues
  • Custom Toolbars and Buttons
  • Custom Dialog Windows
  • 64-Bit Arithmetic
  • Numeric, Logical and String Operators
  • Direct Access to System States

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Last generated/modified: 09-Feb-2023