TRACE32 Instruction Set Simulator

TRACE32 Instruction Set Simulator for LC130 Core RV32

LA-2821L 1 User Float. Lic. TRACE32 RISC-V Simulator

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TRACE32 Features

TRACE32 Instruction Set Simulators

Integral part of TRACE32
Configurable as system under debug (PBI=SIM)
Allows post-mortem debugging
Tool Qualification Support-Kit (TQSK) available for TriCore and 68K
Software compatible to all TRACE32 tools
OS-aware debugging
Cache simulation (architecture dependent)
Program and data flow trace based on a bus trace protocol
Advanced trace analysis features
Powerful script language
Programming interface for peripheral simulation

Target OS Support

Target OS Support for RV32

FreeRTOS (freeRTOS)
Linux (-)
Zephyr (Zephyr Project)

Software Updates

Full software support is not currently available for LC130. Please request for an Interim build on www.lauterbach.com/tsupport.html

Interim builds are produced on a regular basis and contain all new TRACE32 features;
mainly the support for new chips, new compiler versions or new target OSes. Interim builds only passed basic tests.

Product Information

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Standard Products

LA-2821L

1 User Float. Lic. TRACE32 RISC-V Simulator

Floating license to use the TRACE32 Instruction Set
Simulator for automated tests via script language
PRACTICE or via the TRACE32 Remote API

supports RISC-V

for Windows32, Windows64, Linux32, Linux64
and Solaris, other platforms on request

floating license via RLM (Reprise License Manager)

Please add the RLM HostID of the license server
to your order (please see our FAQ)

TRACE32 Debugger for LC130

Configurations for LC130

TRACE32 Instruction Set Simulator

TRACE32 Features

Target OS Support

Software Updates

Peripheral Definitions and Menus

Manuals

Startup And Demo Scripts

Product Information