RISC-V Tool Table

A comparison between the different hardware-based tools is provided by the RISC-V tool table.

Debugger & Off-Chip Trace TPIU

Adaptation

Adaptation RISC-V Debugger

Target Adaptation for Arm CoreSight TPIU

TRACE32 Features

RISC-V Debugger

Support for JTAG interface (JTAG Debug Transport Module)
Multicore debugging
Debug from reset vector or attach to target without altering its state
Run-control debugging via abstract commands and debug program buffer
Support RV32 and RV64 ISA
Support standard ISA extensions: compressed instructions, floating point, etc.
Flash programming
Easy high-level and assembler debugging
Unlimited number of software breakpoints
Onchip breakpoints on instructions and data (match control trigger)
Display of configuration registers and peripherals at a logical level
Target OS awareness
Script language and API interface

RISC-V Trace

Proprietary SiFive Nexus Trace Solution for RISC-V
Proprietary Tessent Embedded Analytics Trace Solution for RISC-V
Support for both, complete proprietary trace infrastructure and proprietary trace IP integrated into an Arm CoreSight trace infrastructure
Multicore tracing
On-chip trace and various types of off-chip trace ports

Target OS Support

Target OS Support for RV32

FreeRTOS (freeRTOS)
Linux (-)
Zephyr (Zephyr Project)

Software Updates

The TRACE32 Software Updater updates your current TRACE32 installation to the latest release version of TRACE32. It can be used if your current TRACE32 installation is newer than August 2012.

Product Information

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TRACE32 Debugger for E31

Configurations for E31