eSi-RISC Core Debugger


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eSi-RISC Core Ecosystem
Hardware-based Debugger
TRACE32 Debug Features
Details and Configurations


eSi-RISC Core  Debugger
  Highlights
Full high-level and assembler debugging
Full onchip breakpoint support
Multicore debugging
Fully scriptable
Support for ESI-3200


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Information
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eSi-RISC Core Ecosystem


Supported Compilers
Compiler Support

C/C++

  • GNU/GCC (ENSILICA)
  • ELF/DWARF2
 
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Hardware-based Debugger


Target Adaptation for eSi-RISC Core

 
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TRACE32 Debug Features


Multicore Debugging
  • Debugger for all cores of a multicore chip
  • Debugging of application cores, DSPs, accelerator cores and special-purpose cores
  • Debugging of more than 80 core architectures
  • Support for every multicore topology
  • Support for all multicore operation modes
  • Support for AMP and SMP systems
  • Single debug hardware can be licensed for all cores of a multicore chip

High-Level-Language Debugging
  • Supports multiple languages
  • Full support for C++
  • Integrated into TRACE32 environment
  • Supports most compilers and hosts
  • Same user interface on different hosts
  • High speed download
  • Debugs optimized code
  • Display of function nesting
  • Display of linked lists
  • Powerful expression evaluation

Sample-based Profiling
  • Long-time performance analysis for functions
  • Long-time performance analysis for tasks
  • Long-time analysis of the contents of a variable or memory location and more

Script Language PRACTICE
  • Structured Language
  • Menu Support
  • Command Logs
  • Custom Menues
  • Custom Toolbars and Buttons
  • Custom Dialog Windows
  • 64-Bit Arithmetic
  • Numeric, Logical and String Operators
  • Direct Access to System States

 
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Details and Configurations


 
eSi-RISC
ESI-3200    Debug only    Ensilica




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Last generated/modified: 12-Sep-2018