TRACE32® eSi-RISC Core Debugger

eSi-RISC Core Ecosystem

Hardware-based Debugger

TRACE32 Debug Features

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Highlights

	Full high-level and assembler debugging
	Full onchip breakpoint support
	Multicore debugging
	Fully scriptable

Technical Support

eSi-RISC Core Ecosystem

Compiler Support

C/C++

GNU/GCC (ENSILICA)
ELF/DWARF

RTOS Support

Hardware-based Debugger

Target Adaptation for eSi-RISC Core

TRACE32 Debug Features

Multicore Debugging

Debugger for all cores of a multicore chip / multiprocessor system
Debugging of high-performance and real-time cores, DSPs, accelerator and special-purpose cores
Support for every multicore topology
Support for all multicore operation modes
Support for AMP, iAMP and SMP systems
Single debug hardware can be licensed for all cores of a multicore chip / multiprocessor system

High-Level-Language Debugging

Supports multiple languages
Full support for C++
Integrated into TRACE32 environment
Supports most compilers and hosts
Same user interface on different hosts
High speed download
Debugs optimized code
Display of function nesting
Display of linked lists
Powerful expression evaluation

Sample-based Profiling

Long-time performance analysis for functions
Long-time performance analysis for tasks
Long-time analysis of the contents of a variable or memory location and more

Script Language PRACTICE

Structured Language
Menu Support
Command Logs
Custom Menues
Custom Toolbars and Buttons
Custom Dialog Windows
64-Bit Arithmetic
Numeric, Logical and String Operators
Direct Access to System States

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The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 10-Feb-2023