Search results for "v20"
supports NIOS-II includes software for Windows, Linux and macOS requires PowerDebug Module IDC20A debug cable voltage range 1.8V to 3.6V
Converter to connect an Arm Debug Cable V1 (ARM-14) to IDC20A or to connect a newer IDC20A Debug Cable to ARM-14 target connector ARM-14 is an obsolete connector specification, do not use for new designs Former name: ARM Converter ARM-20 to/from ARM-14
Supports Intel XSCALE derivatives. Includes license for trace decoding. Uses IDC20A debug cable, which supports 5-pin standard JTAG, cJTAG (IEEE 1149.7) and Serial Wire Debug (SWD), (0.4V - 5V) Includes software for Windows, Linux and macOS. Requires PowerDebug base module.
Supports Hexagon from Qualcomm Includes license for multicore debugging and trace decoding. Uses IDC20A debug cable, which supports 5-pin standard JTAG, cJTAG (IEEE 1149.7) and Serial Wire Debug (SWD), (0.4V - 5V) Includes software for Windows, Linux and macOS. Requires PowerDebug base module.
MIPI20T-HS Whisker for the use with CombiProbe and MicroTrace. Voltage range: 1.2V...5.0V. Maximum trace port width: 4 pins. Maximum trace bandwidth: 400 MBit/s per trace pin.
Supports ARC EM/HS/EV/VPX, ARC 600/700, ARCtangent-A4/A5 Uses IDC20A debug cable, which supports 5-pin standard JTAG, cJTAG (IEEE 1149.7) and Serial Wire Debug (SWD), (0.4V - 5V) Includes software for Windows, Linux and macOS. Requires PowerDebug base module.
Supports VSPA Uses IDC20A debug cable, which supports 5-pin standard JTAG, cJTAG (IEEE 1149.7) and Serial Wire Debug (SWD), (0.4V - 5V) Includes software for Windows, Linux and macOS. Requires PowerDebug base module. Not supported are the very old 1st Gen. PowerDebug modules LA-7702 (without USB) and LA-7704 (with USB 1.1).
Supports CEVA-X. Uses IDC20A debug cable, which supports 5-pin standard JTAG, cJTAG (IEEE 1149.7) and Serial Wire Debug (SWD), (0.4V - 5V) Includes software for Windows, Linux and macOS. Requires PowerDebug base module.
Converter from IDC20A connector to Altera 10-pin (Byteblaster) or RISC-V 10-pin Target connector pitch can be 2.54mm or 1.27mm (half size)
Supports Xtensa Cores from Tensilica via an ARM JTAG interface Core trace decoding for TRAX (Trace RAM within core logic) included IDC20A debug cable, which supports 5-pin standard JTAG, cJTAG (IEEE 1149.7) and serial Wire Debug (SWD), (0.4V - 5V) Includes software for Windows, Linux and macOS Requires PowerDebug module Requires LA-3763 if 14 pin JTAG (Xtensa) connector is used