Tricore Debugger

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Tricore Debugger
Debugging of all auxiliary controllers: PCP, GTM, HSM and SCR
Debug Access via JTAG and DAP
AGBT High-speed serial trace for Emulation Devices
On-chip trace for Emulation Devices
Debugging for Synopsis virtualizer as frontends
Debug and trace through reset
Cache analysis
Multicore debugging and tracing
Third-party tools cooperation and support
Support for INFINEON
Support for
 PXB4260, TC10GP, TC1100, TC1115, TC1124, TC1128, TC1130, TC1161, TC1162, TC1163, TC1164, TC1165, TC1166, TC1167, TC1182, TC1184, TC1191, TC1193, TC1197, TC1198, TC11IA, TC11IB, TC11IC, TC1337, TC1367, TC1387, TC1387ED, TC1724, TC1724ED, TC1728, TC1728ED, TC1736, TC1736ED, TC1746, TC1762, TC1764, TC1765, TC1766, TC1766ED, TC1767, TC1767ED, TC1768, TC1775, TC1782, TC1782ED, TC1784, TC1784ED, TC1791, TC1791ED, TC1792, TC1793, TC1793ED, TC1796, TC1796ED, TC1796L, TC1797, TC1797ED, TC1798, TC1798ED, TC1910,
> more
For more than 15 years Lauterbach TRACE32 tools have been supporting the Infineon TriCore microcontrollers. The established single core TriCore AUDO devices are supported as well as the latest AURIX multicore architecture.

Beside the standard single core and multicore debug features on- and off-chip trace information can be recorded and evaluated. TRACE32 allows programming the MCDS on-chip resources for triggering on specific events or filtering the trace output already on chip level.

Operation Voltage
Frequently Asked Questions
Technical Support

Demo Software for Download


Debug Features

Trace Features

  • Multicore tracing via on-chip trace for Emulation Devices
  • Medium speed multicore off-chip tracing via DAP interface with up to 128 MB trace memory, if necessary long-term trace by streaming to the host
  • Multicore off-chip tracing via high-speed serial AGBT interface with up to 4GB trace memory, if necessary long-term trace by streaming to the host
  • Performance profiling and qualification, e.g. Cache analysis, Code coverge

Software-only Debugging


Multicore Debugging

TRACE32 allows multicore debugging for up to three TriCore cores and all auxiliary controllers.
  • The cores can be started and stopped synchronously
  • The state of all cores can be displayed side by side
  • All cores can be controlled by a single script


Debug Port Sharing with 3rd Party Tools

Some third-party tools access the target using the JTAG or DAP debug port as well. Using such a tool simultaneously with TRACE32 tool requires sharing the debug port between both tools. The following port sharing technologies are supported:

Port Sharing by Using the XCP Protocol

Hardware-assisted Port Sharing

  • Supports sharing the JTAG or DAP debug port with 3rd party tools, e.g. ETAS ETK, dSpace GSI and Vector VX1000
  • Debug port is switched automatically between 3rd party tool and TRACE32 tool
  • Usage of on-chip resources can be restricted to allow concurrent use of 3rd party tool

    Benchmark Counters

    Benchmark counters are on-chip counters that count specific hardware events. A typical example are counters for cache hits and misses allowing the calculation of the corresponding performance metrics.
    • Configuration and observation of
      • On-chip performance counters of cores, counting, e.g., executed instructions, cache hits and cache misses, CPU stalls, ...
      • MCDS event counters on Emulation Devices, supporting, e.g., user events, access counters for various memories, ...
    • Periodically read-out of counters during runtime (Snooper)
    • Start and stop of counters using on-chip triggers to allow fine-grained investigation of single code part

    Debug and Trace Through Reset

    Microcontroller applications are often secured by an internal and/or external watchdog or internal surveillance. In case of any unrecoverable error these systems reset the microcontroller in order to bring it back into a known and safe state. When such a reset occurs during development, the engineers want to know why this error happens, and often how post-error handling after reboot behaves.
    • The debugger is able to detect the reset event and to reconnect to the device after the reset has been released again. The user can configure the debugger′s behaviour in this case: halt target at reset vector or resume application. The debug resources, e.g. on-chip breakpoints, trace and trigger configuration are reprogrammed.
    • In case trace recording was enabled the information of what happened prior to the reset is contained in the trace and can be displayed even after the reset. If the debugger is programmed to resume program execution the trace will continue recording (not possible for on-chip trace in case of a hard reset, e.g. PORST).
    Debug and trace through reset are supported by the Bi-directional and Automotive debug cables.  

    MCDS Trace Message Generation and Trigger

    The MCDS module of the Emulation Devices generates information on the instruction execution and data accesses of up to two cores in parallel as well as transfers on the on-chip buses.

    • MCDS is used for generating unfiltered and filtered trace messages
    • Support for tracing of up to two TriCore cores or an auxiliary core (GTM or PCP):
      • Program flow or sync trace (generating trace messages on branches or on every MCDS clock cylce)
      • Data trace: write address and data, read address (device dependent)
      • Ownership information, e.g. PCP channel ID (device dependent)
    • Support for tracing the processor bus (LMB, SRI) and the peripheral bus (SPB, RPB)
      • Data trace: read/write address and data, ownership information, e.g. bus master, DMA channel, supervisor mode
      • SRI trace allows tracing of data transfers to up to two SRI bus slaves in parallel
    • Pre-defined filter setups, e.g. for OS-aware trace
    • Trace through reset support

    On-chip Trace

    The on-chip trace stores the trace information generated by the MCDS into a trace buffer of the Emulation Device. With its configurable size of up to 1 MB it is perfect for detailed troubleshooting and in-field testing. Filters and triggers allow an effective usage of the trace memory.
    • Up to 1 MB of configurable on-chip trace memory
    • Trigger and filter programming for an efficient use of the trace buffer
    • Configurable on-chip memory allows a concurrent usage of the on-chip trace with third-party usage, e.g. calibration tools or the user application
    • Fully supported by standard debugger, no additional hardware required

    Off-chip Trace

    When information about program execution and data access by cores and/or buses are provided at external pins this information can be stored by the trace tool. It allows detailed qualification and analysis with its up to 4GB trace buffer and the possibility of streaming to the host storage.

    While many TriCore AUDO devices have a parallel trace port most of the TriCore AURIX Emulation Devices support the AGBT high-speed serial trace using the Aurora protocol.

    TriCore Parallel Trace
    • 3.3 Volt Support
    • Trace up to 180 MHz
    • Up to 4 GByte trace memory
    • 16 Channels
    • Timestamp
    • Delay Counter
    • Performance Analysis
    • Code Coverage
    • Fast Search and Upload

    TriCore AGBT High Speed Serial Trace
    • Robust trace recording using Aurora
    • Up to 6.25 GBit/s per lane
    • Up to 4 lanes
    • Up to 4 GByte trace memory
    • Streaming to host storage
    • Delay counter
    • Fast search and download
    • Code Coverage
    • Performance Analysis

    CombiProbe for TriCore DAP
    • Support for 2-pin DAP and 3-pin DAP in wide mode
    • DAP clock up to 160MHz
    • 26-pin automotive connector
    • Same debug features as TriCore Debug Cable
    • 128 MB of trace memory for DAP Streaming
    • DAP Streaming with up to 30 MByte/s
    • DAP Streaming for filtered tracing, GTM tracing and Compact Function Trace
    • TRACE32 Streaming for long-time recording


    Cache Debugging

    The instruction and data caches on TriCore devices can be accessed with TRACE32.
    • For each cache line the valid bit and LRU information is available, data caches additionally provide the dirty bit
    • Cached memory regions can be highlighted in the respective windows, e.g. the Data.dump or the window.
    • When debugging, TRACE32 can be configured to transparently display variable values from the cache (i.e. from the CPUs point of view)
    • In-depth cache analysis is provided with the CACHE. command group

    SCR Debugger

    The Standby Controller (SCR) is an 8-bit microcontroller that can continue to run during the standby mode. It is based on the XC800 core that is compatible with the industry standard 8051 processor. It includes an On-chip Debug Support (OCDS) unit for software development and debugging of XC800-based systems via single pin DAP interface. For the moment it is implemented on the TC2X cores.
    XC800 Debugger
    • Fast hll and assembler debugging
    • Interface to all standard compilers
    • Full support for all on-chip breakpoints
    • Unlimited number of software breakpoints
    • Display of internal and external peripherals at a logical level
    • Flash programming
    • Interface to all hosts
    • Batch processing by script language PRACTICE


    GTM Debugger

    The debugger for the General Timer Modul (GTM) is a free add-on to the debugger for AURIX family and will be accessed in a separate instance of the TRACE32 software.
    GTM Debugger (TriCore)
    • Full debug support of GTM
    • GTM debug support included in the TriCore debug license
    • GTM trace - MCS (Multi Channel Sequencer)
    • GTM trace - ARU (Advanced Routing Unit)
    • GTM trace - I/O channels
    • GTM trace support included in the MCDS trace license


    PCP Debugger

    The debugger for the Peripheral Control Processor (PCP) is a free add-on to the debugger for AUDO family and will be accessed in a separate instance of the TRACE32 software.
    PCP Debugger (TriCore)
    • Full HLL support
    • Disassembler for PCP Instructions
    • Supports ELF/DWARF format
    • Batch Processing
    • Debug Access via JTAG and DAP
    • 3.3 Volt Support
    • Unlimited Software Breakpoints on Code
    • Emulation Device support (additional triggers via MCDS)
    • PCP debugging comes for free with TriCore OCDS Debugger
    • PCP tracing
    • PCP tracing come for free with Preprocessor TriCore OCDS-L2



    Flyer "Debug & Trace for TriCore"  


    A variety of adaptors and converters are available for the connection between debug cables and targets.

    Adaption for Automotive Debug Cable

    • Supports debugging using DAP and JTAG
    • Half Size (1.27 mm pitch) target connector with 10-/20- and 26-pins (AUTO10/AUTO20/AUTO26)
    • Many adaptators available including ECU14 and 16-pin OCDS connector

    Adaption for Standard TriCore Debug Cable

    • Supports debugging using DAP and JTAG
    • 16-pin OCDS target connector
    • Many adaptators available including ECU14 and 10-pin DAP


    IDE - Integrated Development Environment


    Details and Configurations

    Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
    The information presented is intended to give overview information only.
    Changes and technical enhancements or modifications can be made without notice. Report Errors
    Last generated/modified: 19-Oct-2016