Cortex-A ARMv7 JTAG Debugger


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Cortex-A JTAG Debugger (ARM Cortex A)
  Highlights
Easy high-level and assembler debugging
Interface to all compilers
OS awareness debugging
Display of internal and external peripherals at a logical level
Flash programming
Powerful script language
Support for CoreSight components like Debug Access Port, Trace Funnel, Trace Port Interface Unit, Embedded Trace Buffer, Cross Trigger Interface, Cross Trigger Matrix, System Trace Port, Trace Memory Controller
Real-time access to system memory and peripheral registers through Debug Access Port without halting the core
Multicore debugging
Multiprocessor debugging
Software compatible to all TRACE32 tools
High-Speed download
Support for
 AD, ALLWINNER, ALTERA, ARM, ATMEL, BROADCOM, CORTINA, CYPRESS, HILSCHER, LSI, MARVELL, MICROCHIP, NVIDIA, NXP, QUALCOMM, RENESAS, SAMSUNG, SILICONMOBILITY, SOCIONEXT, STERICSSON, STM, TI, XILINX

66AK2E02, 66AK2E05, 66AK2H06, 66AK2H12, 66AK2H14, 88F6707, 88F6710, 88F6810, 88F6820, 88F6828, 88F6W11, A20, A9500, A9540, ADSP-SC570, ADSP-SC571, ADSP-SC572, ADSP-SC573, ADSP-SC582, ADSP-SC583, ADSP-SC583W, ADSP-SC584, ADSP-SC584W, ADSP-SC587, ADSP-SC589, AM3352, AM3354, AM3356, AM3357, AM3358, AM3359,
> more


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[www.arm.com]  CoreSight On-chip Debug & Trace IP
Video: Synchronized AMP Debugging with ARMĀ® and NiosĀ®-II




 
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Adaptation


Adaptation for ARM Debug Connector

Adaptation for MIPI Debug Connectors (ARM)

 
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IDE - Integrated Development Environment


 
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Software Trace Tools


ETB Trace
  • Compatible to external ETM Trace
  • Readout through JTAG
  • No Speed Limit
  • Full Trace of Code and Data

 
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ETM Hardware Trace Tools


Off-chip Parallel Trace
  • Up to 4 GByte trace buffer
  • Target voltage 1.2 .. 3.3 V
  • 5 ns time stamp
  • Program and data trace
  • Performance analysis
  • Function and task run-time measurement
  • Code coverage
  • Support for Embedded Trace Macrocell (ETM), Program Trace Macrocell (PTM)
  • Support for Embedded Trace Buffer (ETB), Trace Memory Controller (TMC), Trace Port Interface Unit (TPIU)
  • Support for multiple trace sources in a single stream (CoreSight trace)

Off-chip Serial Trace via Serial Preprocessor
  • Support of High-Speed Serial Trace Port (ETM-HSSTP, ARM specified)
  • Compatible to Xilinx Aurora protocol
  • Support of up to four differential lanes
  • Maximum 6,25Gbit/s lane speed
  • Up to 4 GByte trace buffer size, sufficient for up to 24 Giga CPU cycles

Off-chip Serial Trace via PowerTrace Serial
  • 4 GByte trace memory
  • Up to 12.5 Gbit/s per channel
  • Aurora-based trace protocols up to 8 RX lanes
  • PCIe-based trace protocol up to 8 RX/TX lanes
  • Reference-clock and bit-clock support
  • Fast trace upload to the host computer
  • Additional independent 17 channel logic analyzer

 
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Details and Configurations






Copyright © 2017 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 10-Jul-2017