Product Catalogue

supports Xtensa Cores from Tensilica includes software for Windows, Linux and MacOSX requires Power Debug Module debug cable with 14 pin connector

Supports Xtensa Cores from Tensilica. Core trace decoding for TRAX included. Please add the base serial number of your existing debug cable or CombiProbe to your order.

supports Xtensa Cores from Tensilica via an ARM JTAG interface core trace decoding for TRAX (Trace RAM within core logic) included includes software for Windows, Linux and MacOSX requires Power Debug Module IDC20A debug cable requires LA-3763 if 14 pin JTAG (Xtensa) connector is used

Supports Xtensa Cores from Tensilica via an ARM JTAG interface Core trace decoding for TRAX (Trace RAM within core logic) included IDC20A debug cable, which supports 5-pin standard JTAG, cJTAG (IEEE 1149.7) and serial Wire Debug (SWD), (0.4V - 5V) Includes software for Windows, Linux and macOS Requires PowerDebug module Requires LA-3763 if 14 pin JTAG (Xtensa) connector is used

Floating license, for connecting the TRACE32 front end for Xtensa to various 3rd party interfaces, for debugging simulators, emulators and virtual targets, as well as physical targets via USB. Supports the following interfaces: * Multi-Core Debug API (MCD) * GDB over Remote Serial Protocol (RSP) * Generic Transactor Library (GTL) (requires license LA-8983L) * Tessent Embedded Analytics via USB (requires license LA-8977L) * Intel® DCI.DbC (requires license LA-8968L). Supports the Cadence Tensilica Xtensa core architecture. For trace decoding please add license LA-9002L. For AMP multicore setups please add license LA-8902L. Floating license via RLM (Reprise License Manager). Please add the RLM HostID of the license server to your order.