Trace Analyzer for Xtensa® (TRAX)

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Trace Protocol
Trace Infrastructure for Xtensa Core
Xtensa Cores in an Arm CoreSight Trace Infrastructure
Generic Trace Features

Trace Analyzer for Xtensa® (TRAX)
Based on Nexus message protocol
Instruction trace
Data trace (configurable while core creation)
Timestamps (configurable while core creation)
Multicore tracing
Custom instructions require libraries for trace decoding
Support for onchip trace and integration into an Arm CoreSight trace infrastructure
Support for NXP


Trace Protocol

Xtensa cores use a Nexus 5001 compliant trace protocol. Supported are:
  • Nexus messages on indirect branches
  • Nexus messages on read/write (configurable while core creation)
  • Timestamps (configurable while core creation)
Custom instructions need libraries for trace decoding, these are typically already loaded during debugging for disassembling the program memory contents.

Instruction/data trace messages may optionally contain a timestamp field. These timestamps are the only way to get time information for the onchip trace. If the trace is recorded with a TRACE32 Trace Module, the Nexus Messages receive their timestamps by the recording tool.

Trace Infrastructure for Xtensa Core


In a multicore chip, each Xtensa core has its own trace RAM. The size of the Trace RAMs is configurable while core creation. The typical size is 4 KBytes.

TRACE32 Tools

TRAX Onchip Trace RAM

Xtensa Cores in an Arm CoreSight Trace Infrastructure


TRACE32 Tools

Onchip Trace (ETB/ETF) Off-chip Trace Port (TPIU) Off-chip Trace Port (HSSTP)

Target Adaptation for Arm CoreSight TPIU

Adaptation for CoreSight HSSTP


Generic Trace Features

Trace-based Profiling
  • Detailed analysis of function run-times
  • Detailed analysis of task run-times and state
  • Graphical analysis of variable values over the time
  • Analysis of the time interval of a single event (e.g. Interrupt)
  • Analysis of the time interval between 2 defined events

Trace-based Code Coverage
  • Real-time code coverage without instrumentation
  • Suitable for long-term testing
  • Support for all common code coverage metrics
  • Automated report generation
  • Full support of multicore chips

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Last generated/modified: 11-May-2022