Xtensa cores use a Nexus 5001 compliant trace protocol. Supported are:
- Nexus messages on indirect branches
- Nexus messages on read/write (configurable while core creation)
- Timestamps (configurable while core creation)
Custom instructions need libraries for trace decoding, these are typically already loaded during debugging for disassembling the program memory contents.
Instruction/data trace messages may optionally contain a timestamp field. These timestamps are the only way to get time information for the onchip trace.
If the trace is recorded with a TRACE32 Trace Module, the Nexus Messages receive their timestamps by the recording tool.
In a multicore chip, each Xtensa core has its own trace RAM. The size of the Trace RAMs is configurable while core creation. The typical size is 4 KBytes.
TRACE32 Tools
Trace Protocol
