TriCore™ AURIX™ Trace


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TRACE32 Trace Solutions
MCDS Trace Features
Generic Trace Features


DEMONSTRATOR LEDA METIS

TriCore™ AURIX™ Trace
  Highlights
Based on MCDS trace protocol
Multicore tracing of up to 6 TriCores, PPU (ARC), GTM and PCP
Instruction trace
Data trace
Trace of transfers via on-chip buses and interconnects
Tool and chip timestamps

On-chip trace for product- and emulation devices
High-speed serial trace for Emulation Devices (AGBT/SGBT)
DAP streaming for CombiProbe

Comprehensive profiling of functions, tasks, data etc.
AUTOSAR-aware profiling
Code coverage measurement for functional safety

Trace for Synopsys Virtualizer Development Kit (VDK)
Trace via XCP
Tool Qualification Support Kit (TQSK) for TRACE32 Instruction Set Simulator TriCore


Link
TriCore Debugger




 

TRACE32 Trace Solutions


On-chip Trace

The MCDS module of the TriCore device generates information on the instruction execution and data accesses of up to six cores in parallel as well as on transfers on the on-chip buses and interconnects. This information is stored into the onchip trace buffer.
  • Up to 2 MB of on-chip trace memory
  • Trigger and filter programming for an efficient use of the trace buffer
  • Configurable on-chip memory allows a concurrent usage of the on-chip trace with third-party usage if necessary, e.g. calibration tools or the user application
  • Fully supported by TRACE32 Debug Cable, approriate trace licenses required

Off-chip Trace

If the information generated about program execution and data access by cores/buses is conveyed to a serial trace port, it can be recorded by a TRACE32 Trace Tool. This allows detailed qualification and analysis with its up to 8 GB trace buffer and includes the possibility of streaming to the host storage.
Off-chip Serial Trace via Serial Preprocessor
  • Support of AGBT, SGBT
  • Robust trace recording using Aurora
  • Support of up to four differential lanes
  • Maximum 6,25 Gbit/s lane speed
  • Up to 8 G Byte trace memory
  • Streaming to host storage

Off-chip Serial Trace via PowerTrace Serial
  • 4 GByte trace memory
  • Universal module that is prelicensed for a trace protocol on delivery
  • Additional trace protocol licenses can be added
  • Up to 12.5 Gbit/s per lane
  • Maximum bandwidth of 100 GBit/s
  • Aurora-based trace protocols up to 8 RX lanes
  • PCIe 3.0-based trace protocol up to 8 RX/TX lanes
  • Reference-clock and bit-clock support
  • Fast trace upload to the host computer
  • Support for TRACE32 Streaming up to 400 MByte/s
  • TRACE32 Standard Probe option
  • TRACE32 Analog Probe option

DAP Streaming

DAP Streaming means that the contents of the onchip trace memory is streamed to the TRACE32 CombiProbe while the program execution is running. As a medium bandwidth trace, the CombiProbe is the matching tool for AUTOSAR-aware profiling, Compact Function Trace and filtered data tracing.
CombiProbe 2 for TriCore DAP
  • Debug cable and 512 MByte of trace memory
  • Whisker cable with 26-pin automotive connector
  • Same debug features as the TRACE32 Debug Cables for TriCore
  • 512 MB of trace memory for DAP Streaming
  • DAP Streaming with up to 30 MByte/s
  • DAP streaming requires a DAP mode, for performance reasons, we recommend DAPWide at 160 MHz
  • DAP Streaming for filtered tracing, GTM tracing and Compact Function Trace
  • TRACE32 Streaming for long-time recording

 

MCDS Trace Features


Trace Message Generation

The MCDS module of the TriCore device generates information on the instruction execution and data accesses of up to six cores in parallel as well as on transfers on the on-chip buses and interconnects.
  • Unfiltered and filtered trace messages
  • Tracing of up to 6 TriCores, PPU (ARC), GTM and PCP (device dependent):
    • Program flow or sync trace (generating trace messages on branches or on every MCDS clock cylce)
    • Data trace
    • Ownership information, e.g. PCP channel ID
  • Support for tracing the processor buses such as LMB, SRI
  • Support for tracing the peripheral buses such as SPB, RPB
  • SRI trace allows tracing of data transfers to up to two SRI bus slaves in parallel

Trace Through Reset

Microcontroller applications are often secured by an internal and/or external watchdog or internal surveillance. In case of any unrecoverable error these systems reset the microcontroller in order to bring it back into a known and safe state. When such a reset occurs during development, the engineers want to know why this error happens, and often how post-error handling after reboot behaves. If trace recording was enabled the information of what happened prior to the reset is contained in the trace and can be displayed even after the reset. If the debugger is programmed to resume program execution the trace will continue recording (not possible for on-chip trace in case of a hard reset, e.g. PORST).

Complex Trigger Language CTL

Complex test scenarios require precisely targeted triggers and filters. These can be configured intuitively with the CTL trigger language.



The screenshot above shows the following use case: According to the specification the interrupt stmlr1T0 is only allowed to interrupt the function workSeries twice. The CTL trigger program now ensures that the program execution is stopped immediately as soon as this specification is violated.
 

Generic Trace Features


Trace-based Debugging (CTS)
  • Allows re-debuggging of a traced program section
  • Provides forward and backward debugging capabilities
  • High-level language trace display including all local variables
  • Timing and function nesting display
  • Has the ability to fill most trace gaps caused by the limited bandwidth of trace port

Trace-based Profiling
  • Detailed analysis of function run-times
  • Detailed analysis of task run-times and state
  • Graphical analysis of variable values over the time
  • Analysis of the time interval of a single event (e.g. Interrupt)
  • Analysis of the time interval between 2 defined events

Trace-based Code Coverage
  • Real-time code coverage without instrumentation
  • Suitable for long-term testing
  • Support for all common code coverage metrics
  • Automated report generation
  • Full support of multicore chips





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Last generated/modified: 20-Jan-2022