The UltraSoC Trace Encoder generates instruction execution details based on an UltraSoC proprietary trace protocol.
The protocol includes an optional timestamp field. These timestamps are the only way to get time information for the onchip or the USB trace.
If the trace is recorded with a TRACE32 Trace Module, the timestamps are generated by the module.
Pure UltraSoC Trace Infrastructure
The UltraSoC trace infrastructure IP can be integrated into any RISC-V based chip.
 TRACE32 Trace Tools
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USB Protocol
- TRACE32 RISC-V FrontEnd (floating license)
- TRACE32 RISC-V UltraSoC Debug BackEnd (floating license)
- TRACE32 MultiCore License (floating license)
- TRACE32 RISC-V Trace License (floating license)
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RISC-V with UltraSoC Trace Components in an Arm CoreSight Trace Infrastructure
The UltraSoC trace infrastructure IP can be integrated into the CoreSight trace infrastructure.
TRACE32 Trace Tools
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Onchip Trace (ETB/ETF)
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Off-chip Trace Port (HSSTP)
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- Allows re-debuggging of a traced program section
- Provides forward and backward debugging capabilities
- High-level language trace display including all local variables
- Timing and function nesting display
- Has the ability to fill most trace gaps caused by the limited bandwidth of trace port
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- Detailed analysis of function run-times
- Detailed analysis of task run-times and state
- Graphical analysis of variable values over the time
- Analysis of the time interval of a single event (e.g. Interrupt)
- Analysis of the time interval between 2 defined events
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- Provides all metrics for functional safety
- For standard trace protocols TRACE32 Code Coverage gets by with no or very little instrumentation, full instrumentation as fallback
- Suitable for long-term testing
- Automated report generation in multiple exchange formats
- TRACE32 Trace-Based Code Coverage is included in the scope of delivery of all TRACE32 Debug & Trace Tools at no additional cost
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Trace Protocol
