DesignWare ARC Trace


The embedded tools company
Nexus 5001 Compliant Trace Protocol
Trace Infrastructure for Chips with only ARC Cores
ARC Cores in an Arm CoreSight Trace Infrastructure
Generic Trace Features


DesignWare ARC Trace
  Highlights
Based on Nexus message protocol (small, medium or full)
Program, data and register trace
Trace protocol may include timestamps or cycle count
Multicore tracing
Trace filter allow to reduce the generation of trace messages
ARC-only trace or integrated into an Arm CoreSight trace infrastructure
Onchip trace, parallel Nexus trace port, CoreSight TPIU, Arm HSSTP
Support for ARC-EM11D, ARC-EM4, ARC-EM5D, ARC-EM6, ARC-EM7D, ARC-EM9D, ARC-HS34, ARC-HS36, ARC-HS38, ARC-HS44, ARC-HS45D, ARC-HS46, ARC-HS47D, ARC-HS48




 

Nexus 5001 Compliant Trace Protocol


Three expansion stages are possible for the trace logic.
  • Small: Instruction trace only
  • Medium: Instruction and data trace
  • Full (rarely implemented): Instruction, data and register trace (read and write to auxiliary registers and write only to core registers)
The execution of conditional non-branch-instructions is also output thanks to branch-history.
 

Trace Infrastructure for Chips with only ARC Cores


Support

TRACE32 Trace Tools

Onchip Trace Off-chip Trace Port (Parallel Nexus)

Nexus Target Adaptation for DesignWare ARC Trace

 

ARC Cores in an Arm CoreSight Trace Infrastructure


Support

TRACE32 Trace Tools

Onchip Trace (ETB/ETF) Off-chip Trace Port (TPIU) Off-chip Trace Port (HSSTP)

Target Adaptation for Arm CoreSight TPIU

Adaptation for CoreSight HSSTP

 

Generic Trace Features


Trace-based Debugging (CTS)
  • Allows re-debuggging of a traced program section
  • Provides forward and backward debugging capabilities
  • High-level language trace display including all local variables
  • Timing and function nesting display
  • Has the ability to fill most trace gaps caused by the limited bandwidth of trace port

Trace-based Profiling
  • Detailed analysis of function run-times
  • Detailed analysis of task run-times and state
  • Graphical analysis of variable values over the time
  • Analysis of the time interval of a single event (e.g. Interrupt)
  • Analysis of the time interval between 2 defined events

Trace-based Code Coverage
  • Real-time code coverage without instrumentation
  • Suitable for long-term testing
  • Support for all common code coverage metrics
  • Automated report generation
  • Full support of multicore chips





Copyright © 2020 Lauterbach GmbH, Altlaufstr.40, 85635 Höhenkirchen-Siegertsbrunn, Germany   Impressum     Privacy Policy
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 17-Jul-2020