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supports Xtensa Cores from Tensilica
via an ARM JTAG interface

core trace decoding for TRAX (Trace RAM within core logic) included

includes software for Windows, Linux and MacOSX

requires Power Debug Module

IDC20A debug cable

requires LA-3763 if 14 pin JTAG (Xtensa) connector is used






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Last generated/modified: 07-Nov-2022