News - TRACE32 supports UltraSoC Trace Encoder IP for RISC-V


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Höhenkirchen-Siegertsbrunn, 10-Jun-2020


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TRACE32 supports UltraSoC Trace Encoder IP for RISC-V


Lauterbach is pleased to announce support for UltraSoC Trace Encoder IP for RISC-V processors. RISC-V is an Open Source Instruction Set Architecture which supports variable width instructions whilst allowing for the addition of custom instructions. In addition to supporting the 32 bit and 64 bit instruction sets, TRACE32, of course, supports the debugging of custom instructions.

The UltraSoC Trace Encoder allows the target to emit trace packets on each non-linear instruction (for example: branches, jumps, etc.) and each task switch. These trace packets are created without interrupting the execution of the processor. The UltraSoC Trace Encoder supports various 3rd party trace infrastructure blocks to forward the trace messages to an eventual ‘trace sink’, such as a RAM buffer or off-chip trace port. Many of these IP blocks are already supported by TRACE32, allowing system integrators the freedom to choose the best technology to fit their overall design. UltraSoc also provides an ‘UltraSoC USB Communicator’ block which is supported by TRACE32 and allows for debug and trace over a USB port on the target.



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Last generated/modified: 10-Jun-2020