News - Hypervisor level tracing

The embedded tools company

Höhenkirchen-Siegertsbrunn, 29-Aug-2019

Hypervisor level tracing

Lauterbach, the world’s leading manufacturer of embedded debug tools, is pleased to announce a major advance in the debugging of Hypervisor based systems. The TRACE32 debug tool can now be used to trace all components in a Hypervisor based embedded system, as well as debug them.

A Hypervisor is a low-level piece of code, or operating system that allows multiple ‘guest’ operating systems to run on a single piece of physical hardware. Each guest operating system is partitioned and is unaware of the existence of the Hypervisor or the other guest operating systems which share the system with it. Hypervisors are increasingly used in embedded systems, for example in the cockpit of a car: applications that are under the control of an AUTOSAR real-time operating system run in parallel to the infotainment managed by a rich OS such as Linux.

Program flow and data trace are very important items in the embedded engineer’s toolbox. They allow a developer to see the path that has been taken through the code and to step backwards from an error or exception to see the root cause. Tracing from multiple cores allows a developer to easily see the interaction between software executing on disparate processors and readily identify bottlenecks, logic bombs or other errors that may only show up at runtime. Trace filters at task or virtual machine level allow developers to reduce the amount of trace generation to show only areas of interest in the system.

Program flow trace can be timestamped, allowing a picture of how long or how frequently something is executed to be built up. From this data it is also possible to determine code coverage metrics to satisfy the demands of safety certification for embedded systems.

According to Stephan Lauterbach, the General Manager: “The ability to now trace every aspect of a complex Hypervisor based system will provide detailed insight into the behavior of all software components and lead to reduced development time and the production of higher quality devices.”

The Hypervisor trace capability will be available for Arm® Cortex®-A and NXP QorIQ® from September 2019. Hypervisor tracing, which also means multicore tracing, requires high bandwidths from the off-chip tracing interface. Lauterbach's trace tools for parallel and serial trace interfaces operate perfectly for this task.

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Last generated/modified: 29-Aug-2019