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Improved support for DesignWare® ARC® Trace
Lauterbach, the world’s leading debug tools provider, is pleased to announce a major overhaul of support for the tracing of ARC based systems in their TRACE32 debugger. ARC’s SmaRT trace has been supported since 2009 and the new update improves support for DesignWare ARC Trace (aka. RTT v5) which allows trace to be captured via an on-chip memory buffer, a dedicated NEXUS port, or as part of a CoreSight based system.
ARC Trace is available on ARCv2 cores (ARC-EM and ARC-HS) and provides program flow trace by implementing the IEEE 5001 NEXUS Class 3 trace protocol. This trace protocol can also be wrapped in CoreSight ATB packets, allowing mixed trace from ARM and ARC cores in a single SoC. Some cores also provide the option of data trace where a trace packet is generated on a CPU store or load operation. ARC Trace can be routed on-chip to a dedicated block of internal trace memory or off-chip via a parallel NEXUS AUX port or a CoreSight trace sink. The ARC trace can operate in AMP or SMP mode.
ARC Trace RTTv4 has been implemented since September 2018 and the RTTv5 implementation will be available from the September 2019 release of TRACE32. This release is available to Lauterbach customers as part of their standard upgrade policy and included automatically for all new customers using ARC based targets.
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