SH Trace


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GENESIS-2 SH-MOBILE-R SH-MOBILE-R2 SH-MOBILE3

SH Trace
  Highlights
Up to 4 GByte trace memory
Up to 1 GRecords
200 MHz speed
Time stamp
Trace-based debugging
Performance analysis
Coverage analysis
Statistic functions
Graphical trace views
RTOS statistics
Support for
 RX610, RX621, RX62N, RX62T, RX630, RX631, RX63N, SH2A-CORE, SH7083, SH7084, SH7085, SH7086, SH7147, SH7201, SH7203, SH7205, SH7206, SH7211, SH7216, SH72165, SH72166, SH72167, SH7251, SH72531, SH72533, SH72544, SH72544R, SH72545, SH72546, SH72546R, SH72567, SH725xxx, SH7261, SH7263, SH7264, SH7267, SH7269, SH726A, SH726B, SH7285, SH7286, SH7294, SH7300, SH7315, SH73382, SH7357, SH74504, SH74513, SH7705, SH7706, SH7709A, SH7709BE, SH7709LE, SH7709S, SH7710, SH7712, SH7720, SH7721, SH7722, SH7723, SH7727, SH7729, SH7751, SH7751R, SH7760, SH7761, SH7763, SH7764, SH7770, SH7780, SH7781, SH7785, SH7786, ST40GX1, ST40NGX1, ST40RA166, ST40STB1
 
  Introduction
This high-speed trace module is designed for the trace port of the SH4 (AUD).


Dim
Modules
Adaptions
Dimensions
Freq
Max. Operation Frequency
Volt
Operation Voltage
Order
Order
Information
Support
Technical Support



 
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Trace Modules


PowerTrace II
  • 1, 2 or 4 GByte trace memory
  • Universal trace module, connect to target via architecture-dependent trace probes (parallel or serial preprocessor)
  • Maximum bandwidth of 19,2 GBit/s
  • Fast trace upload to the host computer
  • Support for parallel trace ports with up to 32-bit at 300 MHz DDR
  • Support for serial trace ports, each lane max. 6.5 Gbit/s, but only up to 19,2 GBit/s in total
  • Support for TRACE32 Streaming up to 180 MByte/s, compression allows higher data rates to be achieved
  • PODBUS Express interface to PowerDebug PRO
  • PODBUS and PODBUS Express interfaces to Logic Analyzer modules, e.g. PowerProbe, PowerIntegrator
  • Additional independent 17 channel logic analyzer (with included Standard Probe)
  • Energy Profiling (with optional Analog Probe)

 
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Support Software







Logger
  • Software trace of any size stored in an array structure on the target
  • General trace format provided by TRACE32-PowerView
  • Configuration and display commands provided by TRACE32-PowerView
  • Works as trace with address and data information
  • Works as a program flow trace (SH4, PowerPC)
  • Time stamp possible
  • Predefined algorithms to fill the trace provided by Lauterbach
  • User defined algorithms to fill the trace also possible

Trace-based Debugging (CTS)
  • Allows re-debuggging of a traced program section
  • Provides forward and backward debugging capabilities
  • High-level language trace display including all local variables
  • Timing and function nesting display
  • Has the ability to fill most trace gaps caused by the limited bandwidth of trace port

SmartTrace
  • Fills in missing code
  • Direct branch reconstruction
  • Indirect branch reconstuction with CTS
  • Memory and Register values from CTS

 
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Compatible Debugger


SH Debugger
  • Interface to all compilers in C and C++
  • Unlimited number of software breakpoints
  • Full support for all on-chip breakpoints and trigger features
  • FLASH programming
  • RTOS awareness
  • Statistical performance analysis
  • Branch trace
  • Software trace based on the branch trace for SH4 (unlimited size)
  • Realtime trace based on AUD with up to 2M frames trace depth up to 200MHz
  • Non intrusive trace based performance analysis

 
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Trace Connectors


Adaptation for SH4

 
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Details and Configurations






Copyright © 2018 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany   Impressum     Privacy Policy
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 02-Jul-2018