Frequently Asked Questions (Archive)


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FAQs Archive for C166 Monitor

Questions
Why can target peripherals not be modified by "Data.Set"? (80166)
Why does stepping fails after enabling the interrupts? (80166)

FAQs Archive for Debugger Hardware

Questions
Are the TRACE32 products in compliance with the European Regulation "REACH"?
Are the TRACE32 products in compliance with the European "WEEE" directive?

FAQs Archive for EPROM/FLASH Simulator

Questions
For which applications the ESICON adapter is used?

FAQs Archive for Host Driver Software

Questions
[Linux] How do I use USB with the TRACE32 host driver(s) on Linux?
[Linux] I don't get a popup menu by a right-mouse button click?
[Linux] I receive the error message regarding the shared library "libstdc++.so.5".
[Linux] Why is my USB debugger not detected at all by Linux?
[Linux] Why is no TRACE32 main window coming up under Unix?
[Windows] Why does my PodBus/USB device connected to Windows 7 not work anymore after some time ?
How can I permit 3 GB memory allocation for the TRACE32 task under Windows?
How can I reactivate the old fashioned font usage?
Is it possible to use an interface converter for TRACE32?
TRACE32 says the PerformanceCounter of my PC seems to be buggy. What does this mean?
What do I need to tell my network administrator if Lauterbach support wants direct access to my debugger?
What should I do if I get an error message about missing fonts during driver startup?
Why do I get under Windows 2000 the error message "Entry point HeapSet information could not be found in dynamic Link library Kernel32.dll"?
Why do I get under Windows XP the error message "The procedure entry point EncodePointer could not be located in dynamic link library KERNEL32.dll"?
Why does TRACE32 warn about an obsolete driver?
Why does Windows 7 report "installation failed" when I connect TRACE32 to USB?
Why is my USB debugger not detected at all by Windows or doesn't work anymore?

FAQs Archive for Installation Guide

Questions
How can I remove the TRACE32 USB driver completely from the registry?
How to use silent mode of TRACE32 software installer?
Where is t32tcpusb, mentioned in the training manual?

FAQs Archive for ROM Monitor

Questions
Why does single step or breakpoint not work?
Why does stepping fail, when executing a MOV SP,xxx instruction?
Why does the ROM monitor crash after modification of EPROM?

FAQs Archive for State and Performance Analyzer

Questions
How can I get prestore information?

FAQs Archive for TRACE32 Software

Questions
How can I use a different Editor like UltraEdit instead of PEDIT from TRACE32?
Where do I get the TRACE32 Remote API for C# (C-Sharp)?

FAQs Archive for x186 Monitor

Questions
Why does emulator crash after a target RESET? (80186)
Why does manual break fail? (80186_80386)

FAQs Archive for x386 and x486 Monitor

Questions
Why does manual break fail? (80186_80386)

FAQs Archive for ARC Debugger

Questions
How can I see the auxiliary registers?
I've received the error message "Emulation debug port fail". What has happened?
My target application never reaches the main() function. What's up?
Why does PowerView open a TERM.GATE window automatically?

FAQs Archive for ARM/Cortex Trace (parallel)

Questions
What does FLOWERROR or HARDERROR mean?
What is different between pin 14 (VTref(JTAG)) and pin 12 (VTref(ETM)) on ETM MICTOR connector?
What kind of Maintenance Contract do I need for the AutoFocus-II Preprocessor?
Which function does the EXTRIG on the ETM MICTOR connector have?
Which trace port bandwidth is supported with the different TRACE32 modules and ETM preprocessors?

FAQs Archive for AVR32 NEXUS Debugger and Trace

Questions
Are there modifications of Atmel EVBs for using Nexus trace ?
Is a breakpoint instruction allowed in the code ?
Which impacts regarding real time behavior must be expected if the Nexus trace is activated?

FAQs Archive for ColdFire BDM Debugger

Questions
How do I instrument my source code for selective tracing?

FAQs Archive for Cortex-A ARMv7 JTAG Debugger

Questions
Does TRACE32 need access to the ROM table to read the CoreSight settings?
How to generate and load debug information using a Greenhills Compiler?
Is it possible to set an on-chip breakpoint on a physical address for a processor with enabled MMU?
Is there a register on ARM Cortex cores that can be used by the target program to detect if a debugger is connected?
The CPU selection is set to "NONE" when I try to detect my Arm chip using the command SYStem.DETECT.

FAQs Archive for Cortex-A/-R ARMv8 Debugger

Questions
Does TRACE32 need access to the ROM table to read the CoreSight settings?
How to generate and load debug information using a Greenhills Compiler?
Is it possible to set an on-chip breakpoint on a physical address for a processor with enabled MMU?
Is there a register on ARM Cortex cores that can be used by the target program to detect if a debugger is connected?
The CPU selection is set to "NONE" when I try to detect my Arm chip using the command SYStem.DETECT.

FAQs Archive for Cortex-M (ARMv6/7/8 32-bit) Debugger

Questions
Does TRACE32 need access to the ROM table to read the CoreSight settings?
How to generate and load debug information using a Greenhills Compiler?
The CPU selection is set to "NONE" when I try to detect my Arm chip using the command SYStem.DETECT.

FAQs Archive for Intel~ 86/x64 JTAG Debugger

Questions
Is it possible to set an on-chip breakpoint on a physical address for a processor with enabled MMU?
What is the difference between the executables t32mx86 and t32mx64?

FAQs Archive for MicroBlaze Debugger

Questions
How can I see the debugging (printf) output of my application?
Is there a trace interface for Microblaze cores?
MicroBlaze spontaneously stops while TRACE32 is attached
What can I do about "Error Reading Processor Config Register"?
Why are there no peripheral files (.PER) for Xilinx FPGAs?

FAQs Archive for MPC5xxx and SPC5xx Debugger

Questions
Can I use a longer extension cable?
Can the Nexus port totally be disabled? (NEXUS-MPC5500)
Does TRACE32 NEXUS MPC5XXX support 16 bit MDO operation? (NEXUS-MPC5500)
How to manage external watch dog timer (WDT) control? (NEXUS-MPC5500)
Is there any impact on processing power when using Nexus trace and JTAG debugger? (NEXUS-MPC5500)
Some variables show wrong values or can not be modified during run-time. (MPC55XX/56XX)
SYStem.Option.FREEZE seems not to have any influence on the timers/counters. Is it possible to let the timers/counters run even when a breakpoint is hit or the cores are halted?
The disassembly shows invalid code with many undef/align "instructions". Trace list shows FLOWERRORS. How can I fix this? (MPC55XX)
The external bus interface (EBI) fails when the debugger (JTAG or NEXUS) is connected. (MPC55XX)
There is no debugger access due to a censored device. What can I do? (MPC55XX)
What are the impacts of the Nexus probe during energy measurement? (NEXUS-MPC5500)
What causes "emulation pod configuration error" when trying to start the debug session
What problems can cause that the debugger fails to connect to an XPC56XX EVB motherboard? (MPC56XX)
Why are sometimes certain messages not visible in the trace? (NEXUS-MPC5500)
Why do I get power fail messages, despite target power is correct at the reference pin? (NEXUS-MPC5500)
Why does the debugger display bus errors (question marks) for the internal SRAM or local memories? (MPC5XXX)

FAQs Archive for MPC74XX Debugger

Questions
Is there a workaround for MP7448 chip errata #24? (MPC7448)
SYStem.UP fails with MPC744x/MPC745x or MPC86xx (MPC744X/745X/MPC86XX)
The debugger can not display flash data and/or memory mapped registers, although the target program can access this memory/registers. (MPC744X/745X)
What causes "emulation pod configuration error" when trying to start the debug session

FAQs Archive for MPC86XX Debugger

Questions
SYStem.UP fails with MPC744x/MPC745x or MPC86xx (MPC744X/745X/MPC86XX)

FAQs Archive for NIOS II Debugger

Questions
Analyzer.List/Trace.List doesn't show correct data. What's wrong?
Which preparations are necessary for off-chip trace in a NIOS II design?
Why is my NIOS II stuck at the reset vector and I cannot step away from it?

FAQs Archive for PowerQUICC II/Pro Debugger

Questions
After SYStem.Up or when opening a dump/register window all displayed memory data is invalid (e.g. 0xDEADBEEx) (MPC826x/80/7x/41/42)
The debugger's memory access works after SYStem.UP, but fails after the running the application. What can be the problem? (MPC83XX)
There are few exceptions where SYStem.Option.BASE.AUTO (default setting) does not work: (MPC82XX)
There are few exceptions where SYStem.Option.IP.AUTO (default setting) does not work: (MPC82XX)
What causes "emulation pod configuration error" when trying to start the debug session
When changing the IMMR base address to a new value memory access results in a buserror (for software since 11/2007) (MPC82XX)
When changing the IMMR base address to a new value memory access results in a buserror (for software before 11/2007) (MPC82XX)
Why does the debugger fail to connect to the processor after erasing FLASH memory? (MPC82XX)
Why does the debugger fail to connect to the processor after erasing FLASH memory? (MPC83XX)

FAQs Archive for PowerQUICC III Debugger

Questions
Breakpoints and HLL steps do not work on MPC85XX (MPC85XX_P10XX_P2020_BSC913X)
Breakpoints are not working properly or stop working completely (MPC85XX_P10XX_P2020_BSC913X)
Debugging critical interrupts on MPC85XX (MPC85XX_P10XX_P2020_BSC913X)
I cannot write data to the internal SRAM (MPC85XX_P10XX_P2020_BSC913X)
SYStem.Option.FREEZE seems not to have any influence on the timers/counters. Is it possible to let the timers/counters run even when a breakpoint is hit or the cores are halted?
SYStem.Up does not work on my new board, how can I analyze the problem using the debugger? (MPC85XX_P10XX_P2020_BSC913X)
What causes "emulation pod configuration error" when trying to start the debug session
Why does the CPU stop unexpected after the operating system booted? (MPC8540_MPC8560)
Why does the debugger stop at a wrong address with error message "imprecise debug event" when a breakpoint is set? (MPC85XX_P10XX_P2020_BSC913X)

FAQs Archive for PowerTrace for NEXUS

Questions
How do I correctly connect a Nexus Probe to a PowerTrace unit?
I don't know exactly which signals from MCU must be connected to which signal on the AUX-port connector. Must certain signals be crossed?
Is there any reason why symbol addresses and names are not displayed from the beginning of the trace?
What is the reason for "Incorrect Nexus-POD CPLD revision" message?

FAQs Archive for PPC400 Debugger

Questions
Error message: software breakpoints not possible with current system setting (PPC4XX)
How can I enable access to ISOCM memory in Xilinx VirtexFX chips?
How should I connect TRACE32-ICD JTAG connector to a Xilinx target? What are the correct IRPRE/IRPOST and DRPRE/DRPOST settings? (Virtex-PPC4XX)
How to enable/configure muxed trace interface for TRACE (PPC440GX)
On SYStem.Up I got emulation debug port problem. (PPC4XX)
Stepping over TLBWE instruction result in another program flow as in run mode. (PPC4xx)
The SYStem.Up/InTargetReset doesn't work with an APM86xxx device! The contents of the memory views are wrong. (APM86190_APM86290_APM86491_APM86692_APM86791)
What does a "Protected Access Error" mean? (APM86190_APM86290)
What is the difference between APM86x90 and APM86x90B?
Why do flow errors exist while ML310 tracing works? (Virtex-PPC400)
Why does SYStem.Detect.CPU detect an ApmPacketProSingle/Dual and not the correct CPU derivative. (APM86491_APM86692)
Why does the debugger show only flow errors? (Virtex-PPC400)
Why does the reset vector of the IOP480 not point to the reset vector of the 401 core? (IOP480)

FAQs Archive for PPC600/750 Debugger

Questions
Data/Instruction address breakpoints do not work or stop working at a certain point in target code. (MPC82XX/83XX)
Strange behavior during or after SYStem.Up; Step/Go do not work correctly; External memory flickers
What causes "emulation pod configuration error" when trying to start the debug session
Writing SYPCR has no effect.

FAQs Archive for QDSP6 Debugger

Questions
When attaching to the Hexagon core, I get an error message: "ISDB locked, core not ready". What does this mean and how can I debug my application?

FAQs Archive for QorIQ PowerPC 32/64 Bit Debugger

Questions
SYStem.Option.FREEZE seems not to have any influence on the timers/counters. Is it possible to let the timers/counters run even when a breakpoint is hit or the cores are halted?

FAQs Archive for RAM Trace Port Trace

Questions
How to avoid "TARGET FIFO OVERFLOW" error messages in the trace window? (TMS470/TMS570)
How to unlock the 'RTP' command? (TMS540/TMS570)
What does the error message "Address exceeds maximum size" mean? (TMS470/TMS570)
What does the error message "Internal error: No RAM/Peripheral address defined for this CPU" mean? (TMS470/TMS570)
What does the warning "Entered address has been corrected to match the current blocksize" mean? (TMS470/TMS570)

FAQs Archive for RH850 Debugger

Questions
Is it possible to debug RH850 using JTAG-V850 N-Wire Debugger for V850?
What is the impact of disabling this RDY pin in RH850 target?
When displaying the content of the Data-Flash on my RH850 device, the values in some address are not stable.

FAQs Archive for TriCore Debugger

Questions
After SYStem.Mode Up the target is running and the debugger shows "running (PLL lock wait)". How can I stop program execution?
I cannot connect to my target after installing Version 2018.01.0000092378 or newer
JTAG communication is not possible with some AURIX devices. (AURIX)
My CPU is no longer hold in SYStem.Mode Down after installing version 2018.01.0000092477 or newer
My Infineon TriBoard does not boot and SYStem.Up fails. (AURIX)
Single stepping seems to hang when debugging optimized code.
TRACE32 shows error "ambiguous symbol", what can I do about it? (AURIX)
When setting a read/write breakpoint to a peripheral module the program execution is not stopped.
When single-stepping I always enter the interrupt handler although IMASKASM and IMASKHLL is enabled.
When the CPU has halted the debugger shows "stopped by swevt" or "stopped by tr0evt".
When using on-chip breakpoints, the Memory Protection Registers are overwritten.
When using target based flash programming algorithms, flash is not completely erased or programmed.
Why does the TriCore chip show that an SMU alarm was raised?

FAQs Archive for V850 Debugger

Questions
Is it possible to debug RH850 using JTAG-V850 N-Wire Debugger for V850?




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Last generated/modified: 29-Nov-2019