FAQs for ICE-68360


The embedded tools company

Search FAQs



PDF document ( 57KB / 23-Oct-2019 )


Why does the message "emulation memory refresh fail" appears during change of the PLLCR register? (68360)
Ref: 0016

The ICE-68360 configured with DRAM emulation memory may show this error message at changing the PLLCR register.
Workaround:
    SETUP.REFERR OFF
    SYStem.TimeReq 10.ms


Why does emulation crash when PLL registers are modified? (68360)
Ref: 0022

The CPU stopps its clock for a while until the PLL is oscillating stable at the new clock frequency. For this reason the emulator will detect a "ClockFail", an "Emulation Debug Port Fail" or "Dual Port Fail".
Workaround:
  • Disable ClockFail detection
  • Increase TimeRequest value
  • Increase TimeDebug value
    SYStem.Option TestClock OFF
    SYStem.TimeReq 10.ms
    SYStem.TimeDebug 10.ms


What could be the reason if the trace listing does not work? (68360)
Ref: 0027

The trace does not work if the CPU's CLK01 line is disabled. Please set the "Clock Output 1 Mode" in the "CLKOCR" register to FULL.




Copyright © 2019 Lauterbach GmbH, Altlaufstr.40, 85635 Höhenkirchen-Siegertsbrunn, Germany   Impressum     Privacy Policy
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 14-Nov-2019