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I receive the error "debug port fail" when trying to connect to the target with SYStem.Up or SYStem.Mode Attach.
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| Ref: 0503 |
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A "debug port fail" error message after a
SYStem.Up
or
SYStem.Mode Attach
could have one of the following reasons:
- The selected debug port type (JTAG / LPD4 / LPD1) does not match the Option Bytes (G3-core variants). Please try different debug port types using the command
SYStem.CONFIG DEBUGPORTTYPE
- RDY-line not connected. Please try to set
SYStem.Option.RDYLINE OFF
- The debug signals have a bad quality e.g. reflections on TCK line. Please check the debug signals especiallly TCK with a scope. A serial termination at TCK (e.g. 50..100Ohm) between target an debugger may solve the problem in such cases. Check moreover if the FLMD0 signal is correctly connected.
- JTAG clock is too high (JTAG mode only). Try to icnrease the JTAG clock using the command
SYStem.JtagClock
- The RESET signal of the CPU is not properly connected. Check the voltage level with an oscilloscope. The RESET signal should toggle at SYStem.Up. Check additionally if the CPU is permanently in reset.
- The problem may be caused in some cases by the target application: when a debug tool tries to connect to
the CPU, the application code is already running (not for G4-core variants). Application code may disturb the debug-connection process. A workaround is to patch a jump to the same address at the reset vector.
- Debug interface is locked
- ID-Code-Protection Unit is locked (G3K-core variants only)
- OSCCLOCK and CORECLOCK don't match the target oscillator frequency and CPU Core-Clock (UART mode)
- Wrong baudrate value. Try different values using the command
SYStem.BAUDRATE
Please use the AutoSetup dialog to connect to the target by selecting the menu
RH850 > Auto Setup
or calling the script
~~/demo/rh850/flash/rh850_autosetup.cmm
Please refer for more information to the "RH850 Debugger and Trace" manual:
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Is it possible to debug RH850 using JTAG-V850 N-Wire Debugger for V850?
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| Ref: 0463 |
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No, a different cable is needed. However, it is possible to debug V850 using JTAG-RH850 Debugger. You can find the adequate debug/trace solution by entering the name of your chip in the search bar of Lauterbach website.
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What is the impact of disabling this RDY pin in RH850 target?
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| Ref: 0464 |
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The RDY- signal is a CPU-output-signal which informs TRACE32 when the CPU can accept the next JTAG command. The CPU informs the debugger that it is "READY" for execution of the next command. If SYStem.Option.RDYLINE is OFF, TRACE32 gets the "ready-status" by polling a CPU debug register. This polling-sequence is slower than reading the RDY- signal directly. The performance loss is around 10%. There are no restrictions on debug functionality, all can be done with and without RDY- line.
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When displaying the content of the Data-Flash on my RH850 device, the values in some address are not stable.
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| Ref: 0465 |
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For RH850, "toggling values" is the normal behavior for not-programmed Data-Flash. Reading these addresses will return undefined results. This is also described in the CPU User-Manual.
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