FAQs for QorIQ PowerPC 32/64 Bit Debugger

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SYStem.Option.FREEZE seems not to have any influence on the timers/counters. Is it possible to let the timers/counters run even when a breakpoint is hit or the cores are halted?
Ref: 0416

The SYStem.Option.FREEZE setting just uses the debug related registers to influence the timer / counter behavior when the target enters the debug halted state.
QorIQ CPUs typically offer an additional register in the RCPM, called CTBHLTCR or TTBHLTCR.
If the corresponding bit for a specific core in this register
  • is set to 1, the SYStem.Option.FREEZE setting can handle both: To let the timers run or to freeze them during the core is in the debug halted state.
  • is set to 0, the timers will always be frozen in the debug halted state, regardless of the SYStem.Option.FREEZE setting.

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Last generated/modified: 30-Sep-2022