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Error Message: "emulation pod configuration error"

Ref: 0105
Error message "emulation pod configuration error" after starting the TRACE32 ICD software

This error can have three sources:
  • The CPU selection in the SYStem window does not match the CPU on the target. Check if the selection matches the processor on the target. Try to use auto detection (PPC..XX selection) if available.
  • The CPU detection failed. Check the JTAG connection to the target.
  • The CPU on the target is not supported by the used debugger software release. In most cases there is additional information given in the AREA window.

Single Step over store instruction fails (MPC7448)

Ref: 0339
Is there a workaround for MP7448 chip errata #24?

Due to MPC7448 chip errata #24, the processor may hang when store type instructions are single stepped with a JTAG debugger.

If you encounter this problem while single stepping through code in RAM, there is also a workaround implemented in the debugger. Enable this workaround using the command:
See Processor Architecture Manual for details about this command.

Flash/Memory Mapped Registers Invisible (MPC744X/745X)

Ref: 0206
The debugger can not display flash data and/or memory mapped registers, although the target program can access this memory/registers.

The MPC744X/5X debug controller only supports burst accesses for the debugger. Some devices however, like flash devices or peripherial controllers do not support burst accesses.
There is a workaround, which can be activated using MAP.DENYBURST [address-range]. This workaround enables variable size memory accesses for the given address range. Please be aware that this workaround is very slow. Keep data.list/dump windows as small as possible and select a high JTAG frequency.
This issue is documented in Freescale's MPC74XX chip errata, errata #8 "Variable size memory accesses via COP cannot be performed using the service bus". MPC7448 and newer are not affected.

SYStem.UP fails when FLASH erased (MPC744X/745X/MPC86XX)

Ref: 0280
SYStem.UP fails with MPC744x/MPC745x or MPC86xx

SYStem.UP of MPC744X/5X/MPC86XX can fail if the instruction at the reset address is invalid. This is a side effect of a chip errata (e.g. MPC7448 chip errata #7)

If the FLASH memory at the reset address (0xFFF00100) is not programmed, the CPU will not stop at the reset address. The debugger will print an error message to the AREA window that the CPU stopped at a wrong address (0xFFF00800). In this case, use the sequence:
to stop the CPU.

If the SYStem.UP fails as described above, but it is known that the FLASH is programmed (e.g. boot loader running), usually the problem is that JTAG_HReset resets only the processor, but not other devices on the board, esp. the memory controller. If the memory controller will not be reset, the FLASH contents for the reset address are probably not mapped correctly. Make sure that JTAG_HReset resets processor and memory controller.

Instruction/Data Address Breakpoints do not work (MPC74XX)

Ref: 0186
Data/Instruction address breakpoints do not work or stop working at a certain point in target code.

The instruction/data address breakpoints probably stop working if the target program enables the memory management unit, i.e. MSR_IR and/or MSR_DR bit set to 1.
Solution: Type TRANSlation.ON to the command line. This command will enable MMU support of the debugger, which will configure the on-chip breakpoints properly.

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Last generated/modified: 15-Oct-2019