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Data/Instruction address breakpoints do not work or stop working at a certain point in target code. (MPC82XX/83XX)
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| Ref: 0186 |
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The instruction/data address breakpoints probably stop working if the target program enables the memory management unit, i.e. MSR_IR and/or MSR_DR bit set to 1.
Solution: Type
TRANSlation.ON
to the command line. This command will enable MMU support of the debugger, which will configure the on-chip breakpoints properly.
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Strange behavior during or after SYStem.Up; Step/Go do not work correctly; External memory flickers.
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| Ref: 0131 |
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The !QACK signal is a confirmation input for the CPU.
The signal indicates that no other device will access/use the 603 bus and no bus snoop is necessary by the CPU. Only after this confirmation the CPU changes from user mode back to debug mode.
Normally this signal is served by any external memory controller/bridge or any other logic. In this case the signal needs a pull-up because it's LOW active.
If there is no device using the 603 bus or serving this signal, !QACK must have a pull-down or be tied to GND.
On a target with a MPC107 bus controller, some boot loaders configure the MPC107 so, that !QACK is driven HIGH if it is not asserted. The MPC107 has to be configured to tristate the signal in this case. If the signal is LOW, the debugger is not able to control the CPU properly.
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What causes "emulation pod configuration error" when trying to start the debug session?
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| Ref: 0105 |
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This error can have several sources:
- The CPU selection in the SYStem window does not match the CPU on the target. Check if the selection matches the processor on the target. Try to use automatic detection (SYStem.DETECT CPU).
- The CPU on the target is not supported by the used debugger software version. Please check if a new version is available in the Downloads section.
In any case please check the AREA window (Menu: View - Message Area) for further information.
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Writing SYPCR has no effect.
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| Ref: 0045 |
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The SYPCR register can only be written one time.
If the SYSTEM.OPTION.WATCHDOG is set to OFF then the CPU WATCHDOG function will be disabled by the debugger during a SYSTEM.UP. To disable the WATCHDOG on the CPU the debugger writes to SYPCR and uses the one-time write access to the SYPCR register.
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