FAQs for PPC44X
|How should I connect TRACE32-ICD JTAG connector to a Xilinx target? What are the correct IRPRE/IRPOST and DRPRE/DRPOST settings? (Virtex-PPC4XX)|
This document describes for Xilinx Virtex chips how to:
|How to enable/configure muxed trace interface for TRACE (PPC440GX)|
1. Enable Trace Broadcast:
(! [CTEMS] register bit description in "PPC440GX_UM2001_v1_04.pdf" is upside down!)
|Stepping over TLBWE instruction result in another program flow as in run mode. (PPC4xx)|
There is a difference between stepping and running over a tlbwe instruction sequence.
In run mode, the CPU performs the code as usual, the execution of a tlbwe instruction changes the UTLB contents but does not cause a context synchronization and thus does not invalidate or otherwise update the shadow TLB entries.
Any modification in the UTLB will not be active until the next context synchronizing (ISYNC, RFI, RFCI, SC, interrupts) takes place.
In usual, the application prepare the hole new MMU map, and switch to the new MMU table with a context synchronising instruction at the end of the TLB instruction sequence.
If debug mode, CPU is stopped and the debugger have access to register and memory, each single step forces implicit an ISYNC command. This is a special behavior of the debug mode and mean, with each step a context synchronizing will be forced. Therefore its not possible to step over the standard MMU initialisation sequence.
A recommendation is to set at breakpoint (BP) at the end or after of the TLB init loop. May be at the ISYNC instruction, and run over the TLB setup routine to the BP.
|The SYStem.Up/InTargetReset doesn't work with an APM86xxx device! The contents of the memory views are wrong. (APM86190_APM86290_APM86491_APM86692_APM86791)|
Some Revisions of the APM86xxx family need a special handling for Reset. As a rule of thumb the Revison A e.g. of an APM86x90 requires an SYStem.Option.ResetMode CHIP while the later revisions require an SYStem.Option.ResetMode SYSTEM.
|What does a "Protected Access Error" mean? (APM86190_APM86290)|
Section Memory Controller initialization of User Guide: After Reset the Memory Queue, Memory Controller and DDR PHY are hold in Reset and clocks are disabled. Any request on the PLB Bus designating DRAM or one of the above Peripherals (ERPN 0x0 to 0x3) will cause an infinite stall of the CPU (=>RESET). Furthermore the L2 Cache can not be enables (L2COBE) before the above mentioned Peripherals are out of Reset and working. A such situation is guarded by an "Protected Access Error". The Memory views addressing ERPN 0x0 to 0x3 (PLB5) are unlocked as soon as the clock gating is enabled and the reset is deasserted.
|What is the difference between APM86x90 and APM86x90B?|
Use CPU selection APM86x90 for -> Rev A (primary silicon)
Use CPU selection APM86x90B for -> Rev B,C,D,E (all newer one)
|Why does SYStem.Detect.CPU detect an ApmPacketProSingle/Dual and not the correct CPU derivative. (APM86491_APM86692)|
Many devices of the APM86xxx family share common JtagIDs which do not allow to distinguish between the single derivatives. As a solution a general ApmPacketProSingle/Dual device is detected to allow general debugging.
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Last generated/modified: 28-Nov-2019