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Analyzer.List/Trace.List doesn't show correct data. What's wrong?
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| Ref: 0210 |
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If you enable the off-chip trace for a NIOS II CPU in the SOPC Builder then we recommend to make some manual modifications to your design to improve the reliability of the trace.
This modifications are described in an application note which you can find in your installation directory under pdf/app_nios.pdf.
If you want to try without this modifications you HAVE to enable the "FSS" system option. (For example with the command "System.Option FSS ON").
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Which preparations are necessary for off-chip trace in a NIOS II design?
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| Ref: 0245 |
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Using the off-chip trace in a NIOS II design requires special preparation. This application note explains the steps to implement a reliable off-chip trace port for your NIOS II system:
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Why is my NIOS II stuck at the reset vector and I cannot step away from it?
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| Ref: 0331 |
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Modern NIOS II cores have the option to implement a "cpu_resetrequest" input and a "cpu_resetttaken" output. By asserting "cpu_resetrequest", the NIOS II core can be reset without resetting anything else in the system. The NIOS II core will acknowledge the reset request by asserting "cpu_resettaken", once the NIOS II core has successfully exectued the reset.
The NIOS II debug logic is implemented in such a way, that the debugger can still access a NIOS II core while the "cpu_resetrequest" signal is asserted. So you can examine and modify the processor registers and you also can access memory, while the "cpu_resetrequest" signal is asserted.
The exception to this behavior is the program counter: As long as the "cpu_resetrequest" signal is asserted, the program counter is stuck at the reset vector and the Nios II core will not execute code if you issue a "step" or "go" command.
Also as long as the NIOS II core is stopped (so while the debugger shows that the NIOS II core is not running), the NIOS II core WILL NOT assert the "cpu_resettaken" signal.
Any reset logic reacting to the "cpu_resettaken" signal will NOT receive an acknowledge as long as the NIOS II core is stopped. Reset logic should be designed to handle the case that a NIOS II core is stopped by a debugger and because of that the NIOS II core does not assert the "cpu_resettaken" signal for a long time.
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