FAQs Archive for In-Circuit Emulator for MC68000 and MC6830X

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PDF document ( 129KB / 27-Mar-2022 )

In which way timers and watchdog can be handled when emulation is stopped? (68XXX)
Ref: 0036

By default the timer- and watchdog counters are still enabled if emulation is stopped. To prevent watchdog resets or timer exceptions there are three ways to handle them.
1. Disable them for ever: Please have a look to the CPU Users Manual how to disable the watchdog and timers.
2. Watchdog and timers are enabled but stopped as long as emulation is stopped: There are some CPUs in the 68K family which have a FREEZE pin. The emulator handles this line, which can be used to stop timers. Stopping of timers, watchdog, SDMA or IDMA only works if this CPU option is enabled. The "System Control Register" of the 68302 contains the freeze bits for timers and watchdog. Please have a look to the CPU Users Manual for additional FRZ bits and have a look to the on line help "SYStem.Option FREEZE" command.
3. Exceptions are handled in a Background Task: Please have a look to the online help: "go.back" command, "break.enable back" command.

What could be the reason for wrong addresses in the program counter or analyzer listing? (68LC/PM302)
Ref: 0032

The 68LC302 and 68PM302 (if PCMCIA enabled!) only support addresslines A00--19. The emulator creates the missing addresslines A20..23 by using the chipselect configuration which must be entered to the SYStem window. If the emulator configuration does not match the CPU chipselect configuration, a wrong address will be created which will cause a wrong program counter address, a wrong analyzer display or trouble with mapping and breaking.
To prevent such trouble the emulator and CPU configuration should be done before running program and should not be changed during program execution. If it is necessary to change the chipselect configuration, the program must be stopped to change the configurations by emulator commands and the program part for chipselect configuration must be skipped.
Example for a PRACTICE command file:
   ; configure emulator CS0..3 baseaddresses
   SYStem.Option BR0 value1
   SYStem.Option BR1 value2
   SYStem.Option BR2 value3
   SYStem.Option BR3 value4
   ; configure CPU CS0..3 baseaddresses
   Data.Set 0fff830 %Word value1
   Data.Set 0fff834 %Word value2
   Data.Set 0fff838 %Word value3
   Data.Set 0fff83c %Word value4

What could be the reason for wrong exception vectors? (68302D)
Ref: 0033

The 68302 dual chip module uses two 68302 CPUs. Exception vectors are generated by the slave CPU which is in "disable CPU" mode. After reset no vectors will be generated because the VGE (Vector Generate Enable) of the System Configuration Register is disabled. This bit must be set by the user-program or by a data.set emulator command before the first interrupt is pending.

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Last generated/modified: 30-Sep-2022