FAQs Archive for In-Circuit Emulator for MC68020/30


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PDF document ( 87KB / 02-Jun-2020 )


Is it possible to run emulation out of Target Power Up? (68020)
Ref: 0182

There are different ways to support this:
  • PowerUp detection by a script file
By default the ICE enters SYSTEM.DOWN state as soon as a Target Power Fail is detected. With a script file it is possible to run automatically an init sequence of commands as soon as Target Power Up is detected by the ICE.
Add the following lines to your setup script:
 on powerup gosub
 (
   system.mode emulext
   register.reset
   go
  )
  stop
Of course there is a timeslip between Target Power Up and running the first instruction.
  • Faster version of solution 1 (timeslip about 35 ms)
Setup:
  • Normal setup of emulator and application
  • Then power down target
  • Enter command SYSTEM.Mode StandBy
  • power up target
  • PowerDown-Up during program execution
With this method there is no timeslip between Target Power Up and the execution of the first instruction. The ICE bahaves as the real target CPU.
Setup:
  • Prepare a CPU socket with all VCC pins removed
  • Plug this socket in between target and probe
  • Add the command "SYStem.Option TESTCLOCK OFF" to your setup file
  • Run your application and do a PowerDown-Up sequence
Target PowerDown is no more detected, but program execution restarts by detecting the target RESET-UP.

Is there a PullUp at the emulator Reset Line? (68020)
Ref: 0183

Yes there is a PullUp of 2.7 kOhm to 5 V.
For weak target Reset signals (or at Target Power Down) it might be necessary to modify this pull-up resistors. Please contact the Lauterbach support team.

Is there a restriction in Single Stepping of FPU instructions? (68020)
Ref: 0184

Yes, there is. ASM Single Stepping of FPU instructions will cause wrong FPU results.
Workaround:
Use the Go.Next command/button.
This sets a temporary breakpoint to the next instruction and executes the FPU instruction in realtime.

Problems with STERM bus cycles. (68030)
Ref: 0181

STERM bus cycles are not supported!

Why there is only one record in the trace listing, if the dataselector hits on a misaligned access? (68020)
Ref: 0180

The dynamic dataselector of the ICE68020 detects any data pattern even if the CPU access is split into two buscycles. E.g. a LONG access to address 0x3 is split into a byte access to 0x3 and a tripple access to address 0x4. At the first buscycle (byte access) the data selector logic detects the first part of the data pattern. With the second buscycle (tripple access) the data selector detects the second part of the data pattern and becomes true. The first buscycle is not traced, because at this time the data selector does not "know" if the second part of the data access will hit the selector condition.




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Last generated/modified: 24-Sep-2020