FAQs Archive for In-Circuit Emulator for 8051

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PDF document ( 112KB / 27-Mar-2022 )

Can I map the CPU internal memory externally? (8051)
Ref: 0010

No, not recommended.
The CPU internal programm area must be mapped internally because this memory is an on-chip memory. If the 8051 is in microcontroller mode (EA=1), the program area can never be substituted with a memory on the target. The CPU internal data area can not be mapped externally as well, because there is no access to the internal address and data bus in any case.
But what is the difference between memory which is mapped internally or externally? Only off-chip memory (program or/and data area) can be mapped internally (within the emulator provided emulation memory) or mapped externally (to the user provided memory on the target, external the emulator).

How can I stop the internal watch-dog timer after break? (8051)
Ref: 0011

There are two different ways to stop or to service the internal watch-dog timer for the case, that the watch-dog cannot be disabled by software. It depends on the emulation technique which is used.
If a bond-out chip is used, the customer may choose the IOSTOP option in the SYSTEM control window. After break, all internal peripherals including the watch-dog timer are stopped or inhibited if the option is on.
In a non bond-out system, the watch-dog timer must be serviced after break to prevent a reset. The TRACE32 is able to support any software routines in the background while the emulator has stopped the user programm execution. To achieve that behavior, follow the instruction you will get if you type HELP TASK or on the appropriate pages in the user guide.
This procedure can also be used to keep the emulator active for any interrupt requests after an user programm break.

How do I trace a chip internal data transfer from one register to an other? (8051)
Ref: 0009

Neither a bond-out based nor a non bond-out emulator has access to the internal busses between the registers. Also it is impossible to see any access to or from an internal auxiliary memory area, except the CPU provides special modes. During real time program execution there is no chance to trace these accesses or make decisions depending on the content. During program emulation (not a real time program execution) there are a lot of emulator instructions to verify register or internal memory. As a combination of both, so-called spot breakpoints are available.
Nevertheless the emulator and the analyzer are able to trigger and trace on the access type (e.g. read bit direct) and on the internal addresses of byte direct and bit direct accesses.
There are two different ways for a work-around. But bear mind, it is impossible to trace the value of the EA bit in real time.
1. It is possible to stop the user program by setting a breakpoint to any internal bit or byte address. This causes an asynchronous break of the user program. But consider, the access must be made by an direct access (indirect accesses will not work).
2. It is possible to trigger (also asynchronously) to an internal access using the analyzer. But consider that the internal data transfer can never be seen outside the chip. As long as the access type and the address is known the following trigger program may help (in this example SETB EA and CLR EA):
DATA.B0 ea_adr 0AF ;bit address of EA
DATA.B0 clr_opf 0C2 ;clr EA opfetch
DATA.B0 set_opf 0D2 ;set EA opfetch
LL0: goto LL2 if clr_opf:a:opfetch
cont if set_opf:a:opfetch
LL1: s,mark.a if ea_adr
goto LL0
LL2: s,mark.b if ea_adr
goto LL0
In the analyzer list window, the number and the order of access to the EA bit can be seen.

These are examples, which should only show the way to work-around.

I have some problems using 8051 ports as a bank register. Do you know reasons for that behavior? (8051)
Ref: 0049

If port pins are used as additional address lines for banking purposes, the address lines must be synchronized to the regular addresses. In other case, nobody can predict when the port pins are valid. Refer to the manufactures 8051 manual.

What can cause error messages while real time program execution, if the RESET line is activated or released? (8051)
Ref: 0064

There is a difference in behavior of the original CPU and the emulator. The emulator does not have a Schmitt-Trigger input like the CPU has. In case of problems, it is recommended to check the RESET line: Are there spikes, heavy noise or is the falling or rising slope of RESET slower than 10 us.

What is the difference between a bond-out and a non bond-out emulator? (8051)
Ref: 0008

A bond-out chip provides a lot of additional signals and features which simplify the control of a CPU, like the user program stop, entry to the user program and exit from the user program. Basically however, the bond-out chip provides the addresses, data and the control lines of a CPU internal program area (EPROM, PROM, EE_PROM, FLASH_ROM). As an option, all internal peripherals and interrupt sources can be stopped while the user program has been stopped. Additional registers contain information about pending interrupts etc. Some bond-out chips are "Combi-CPUs" which can emulate more than a derivative of the 8051 family.
A non bond-out emulator uses the original chip, which is readily available their local distributor. There are no additional lines and information available about the internal memory area and there is no direct way to stop internal peripherials or to prevent internal interrupt requests during an user program stop. Special workarounds (provided by the emulator) cater for nearly the same comfort as a bond-out solution. Please bear mind that the program area must be external (EA=0).
Conclusion: If you use a 8051 derivative in microcontroller mode (EA=1) and have not got program memory on the target, then you must choose the bond-out solution. This solution supports both methods of operation EA=0 and EA=1. In the other case, if you use only the microprocessor mode (EA=0) with EPROM on the target, you may choose the non bond-out version.

Which number contains R6 if the bank file is called?
Ref: 0114

The parameter value in R6 of the bank file contains the number of the requested bank. However, it depends on the used bank logic if R6 contains value 1 for the bank 1. A better description is, that R6 contains the same value as the value of the bank probe input lines for the appropriate bank number. If there is a address translation by the MMU command, R6 could contain 3 for bank 1 depending on the address translation.

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Last generated/modified: 02-Jan-2023