FAQs Archive for FIRE Emulator MPC8XX

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PDF document ( 115KB / 27-Mar-2022 )

Are the Low Power Modes available? (MPC8XX)
Ref: 0094

All low power modes are available in general. It is possible to enter the low power mode and exit it through user program. While low power mode is active, no break is possible. The low power mode has to be exited by an user defined event (normaly an interrupt) before a break can be executed.

Are there any usefull tricks to know when debugging with cache. (MPC8XX)
Ref: 0083

The I-cache is considered when displaying data windows
The D-cache is considered when displaying data windows
The I-cache is flushed before a go or step (Necessary for removing the software breakpoints out of the instruction cache after a stop at a program breakpoint)

I get the error message "emulation debug port fail" when activating the system with SYS.MODE EE or SYS.MODE EI in target. (MPC8XX)
Ref: 0097

Probably the CPU gets no CPU clock due to problems of the internal PLL.
To be sure if this is the reason, check the cpuclock in the counter system.
Probably the MODCK configuration, the value of the filter capacitor on the XFC line or the value of the internal VCO don't match.

I get the error message: verify error at address ..., Stepping is possible, Go till is not possible. (MPC8XX)
Ref: 0082

Normaly, the MPC8xx uses software BP as program breakpoints. If it is not possible to patch the code at the requested address, the debugger will display the error message:
verfiy error at address (address)
HLL stepping is done in single stepping mode then: The debugger repeats assembler steps until the cpu reaches the next HLL line.
Reason for impossible write actions are:
1. The target memory is a ROM/FLASH/EPROM
2. The appropriate CS is switched to ReadOnly mode
If there is a read only memory in target, it is not possible to patch the code. Then it is necessary to tell the debugger the addresses where the internal on-chip breakpoints have to be used. Use the instruction:
MAP.BOnchip (addressrange)

I'm using the software emulation interrupt in my code. But every time an SEI occurs the CPU stops and doesn't process my interrupt handler. (MPC8XX)
Ref: 0095

The decision if an interrupt stops the CPU or is processed in the handler is done by the debug enable register of the CPU. To manipulate this register use the Trigger.Onchip. The command is:

My CPU runs fine, but does not stop if I press the break button. (MPC8XX)
Ref: 0099

The fire needs the information if the CPU runs in the user program or has stopped (freeze indication). There are two possibilitys to get the information that the CPU has stopped:
1. VFLS0 and VFLS1 line are high. The VFLS functionality is shared with different signals. To get the VFLS functionality, the debug pin configuration in the system interface unit module configuration register has to be set to 11.
2. The freeze line is high. The freeze functionality is shared with IRQ6. To get the freeze functionality, the FRC bit in the system interface unit module configuration register has to be set to 0.
By default, the VFLS pins are used for freeze indication. To switch the freeze line as freeze indcation, the SYSTEM.OPTION FREEZE has to be switched on.
Check if your software don't overwrite the value of the SIUMCR with a wrong value.

My triggerunit doesn't react on Alpha breakpoints. (MPC8XX)
Ref: 0098

The MPC8xx have a very tricky interface for adapting to different types of RAM. This User Programable Machine (UPM) is used to create a project specific timing for your hardware. If you are using a DRAM, the address lines of the CPU are multiplexed for this memory type. The FIRE emulator is not able to work with this multiplexed address lines.
For internal mapping or setting asynchronous hardware breakpoints, it is necessary that the CPU shows the complete address at the begin of each cycle. Therefore, the CSNT/SAM bit in the option register of the appropriate chip select has to be set to 0.
If this change is done, the timing of your target interface changes, and the setting of the UPM ram has to be changed according to this.

The upper 6 addresses in the trace of the MPC850 are always 0. What can I do to get these addresses become true. (MPC850/823)
Ref: 0086

On the MPC850/MPC823, not all internal address lines are available on the external pins of the chip. For the trace, it is necessary to know the value of each CS Base Register to reconstruct the upper 6 addresslines. Use the
to tell the tool these values.

There are several key registers on the MPC8xx. It seems it is not possible to write the key value 55CCAA33. (MPC8XX)
Ref: 0092

The key registers are no read back registers. So, it is not possible to read the value back you have written to. The function of the key register (to enable/disable the access to the belonging control register) is available.

What happens if I step through my code and an exception occurs? (MPC8XX/5XX)
Ref: 0091

If you step in the main program, an exception will be executed and the cpu returns to your main program (if the software of the exception handler is o.k.) while stepping. So, if you are using a FIRE, you can see the exception in the trace.
If the exception is switched to a debug event in the trigger onchip menu, the debugger will stop on the line and no more stepping is possible.

When running in target memory, the CPU stops suddenly, status line showing stopped by see. (MPC8XX)
Ref: 0088

Possibly, there is a problem of the bus interface between the CPU in the active probe of the emulator and the memory on the target.
1. Check if a data.test is possible in your memory
If possible, check if the CPU performs burst cycles, switch the burst inhibit bit of the appropriate CS on
If not possible, the timing of your target ram is probably very sharp. On UPM timing, try slower settings, on GPCM timing, add a waitstate.

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Last generated/modified: 30-Sep-2022