FAQs Archive for MPC5xx/8xx Debugger
|How do I use the TRAP exeption for my own application? (MPC8XX/5XX)|
Use the command
SYStem.Option NOTRAP ONWith this setting the TRAP exception is no longer used for software breakpoints. UNDEF 0 is used instead.
Use the command
TrOnchip.Set PRIE OFFWith this setting the debug mode is no longer entered when a TRAP occurs. See also the Debug Enable Register in you processor manual.
Now your application can handle the TRAP instruction.
|I get the error message: verify error at address ... (MPCXXX)|
By default TRACE32-ICD uses software breakpoints to set a breakpoint to an instruction. Software breakpoint means the original instruction is replaced by to TRAP in order to stop the program. This is the reason why a software breakpoint usually requires that the instruction is in RAM. Otherwise the error message verfiy error at address (address) is displayed.
The reasons for these errors are:
|Step or go result in an error message! (MPC5XX/8XX)|
... VFLS0/1 pins have wrong status.
Freeze connected?Right after reset VFLS pins are also inputs!
SYStem.Option.FREEZEVFLS from MIOS modul used?
PU is missing 10 kOhm
State is non-recoverable!
|The target runs fine without the debugger attached. But with the debugger attached, the target runs for a while and then it hangs up. (MPC8XX/5XX)|
If the debug mode is enabled, the serialize control bit and the instruction fetch show cycle control bits are set to SERALL after reset.
In SERALL mode the processor is fetch serialized and all internal fetch cycles appear on the external bus. The processor performance is, therefore, much slower. If only a debugger is used perform the command "SYStem.Option IBUS NONE".
In NONE mode the processor works in normal mode and no show cycles are performed. There is no performance degradation in this mode.
If a RISC Trace or a PowerTrace is used, perform the command "SYStem.Option IBUS IND". In IND mode the processor works in normal mode and show cycles are performed for all indirect changes in the program flow. The performance degradation in this mode is about 1 %.
For more information refer to the description of the ISCT_SER register in your processor manual.
|What happens if I debug my code and an exception occurs? (MPC8XX/5XX)|
The MPC8xx/5xx can react in two ways when an exception occurs:
TRACE32 displays the reason for the program stop in the state line (refer also to the Exception Cause Register description in your processor manual).
The program execution is stopped in most cases exactly at the instruction that caused the exception, in some cases at the next instruction.
On some exceptions it is not possible to continue the debugging.
|When stepping with the debugger, the runtime counter shows too long count values. (MPCXXX)|
The runtime counter unit of the PowerPC debugger is realized using a software counter of the host and a hardware counter of the Lauterbach tool. The accuracy is about 10 us.
|Where can I find more information about the acronyms SEIE, PRIE, MCIE, ...? (MPC8XX/5XX)|
These names reflect the bits of the DER Register (Debug Enable Register), ECR (Exception Cause Register for MPC5xx family) and ICR (Interrupt Cause Register for MPC8xx family).
The TRACE32 Debugger evaluate these bits all the time the processor change from running mode to stop status. The abbreviation of these corresponding exceptions/interrups handler differ a little bit between the MPC5xx and MPC8xx family and several sub-derivatives manual.
This could be set up in the T32 PowerView Menue:
Break - OnChip_Trigger - Set - [MCIE] (MCIE is used as example here)or alternatively in the command line or script language:
TrOnchip.Set [MCIE] ONIf the option is enabled (box is checked), the CPU will stop right at the instruction cause this exception/interrupt and enter the debug mode.
|With connected debugger program behaves in a different way (MPC5XX/8XX)|
sys.o.ibus == debug register
ibus has priority, register will be overwritten.
RSTCONF for IBUS will be overwritten.
sys.nodebug only will not enable the BDM interface.
sys.o.freeze.off (default) assumes VFLS0/1 at BDM connector and overwrites SIUMCR bits. (MPC8XX)
|Write access to the ICTRL register by the program does not take any effect! (MPC5XX/8XX)|
If BDM (background debug mode) is enabled, the ICTRL register CAN NOT be modified through the program and can only be modified through RCPU development access (by debugger).
[MPC565 user manual, chapter 188.8.131.52 Program Trace Guidelines]
The BDM is enalbed if the Debugger is connected and CPU is up.
(e.g. SYStem.Mode.Up, SYStem.Mode.Go)
The BDM is disabled even if the debugger is connected when SYStem.Mode.NoDebug is used.
The debug mode will be enable with a DSCK assert HIGH while SRESET asserted.
If there is no debugger connected and there is the same behavior, maybe a pull-up at DSCK causes the BDM automatically.
Note: Use the SYStem.Option.IBUS [xxx] to set the ICTRL[ISCT_SER] bits. Manual access to the ICTRL register (SPR 158./0x9E) will be overwritten by the debugger with each Step or Go!
Copyright © 2021 Lauterbach GmbH, Altlaufstr.40, 85635 Höhenkirchen-Siegertsbrunn, Germany
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 23-Jan-2021