FAQs Archive for MicroBlaze Debugger

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PDF document ( 121KB / 27-Mar-2022 )

FPGA configuration via TRACE32 fails but works with Xilinx Impact.
Ref: 0306

In one case it was observed, that FPGA configuration worked with Xilinx Impact but failed with TRACE32. In this case the target had been set up for FPGA configuration via SPI. This implies the possibility to override the configuration via JTAG.

After jumpering the target for "JTAG dedicated" configuration, downloading the bitstream via TRACE32 worked fine. Note that in the failing case the download failed silenty i.e. jtag.loadbit did not report an error.

In general be sure to set multicore pre/post parameters before configuring the FPGA with identical values as used for debugging.

How are multicore settings calculated?
Ref: 0235

For a description of how to calculate multicore settings (PRE/POST values) for MicroBlaze cores, see the application note "Connecting to MicroBlaze Targets for Debug and Trace" (app_microblaze.pdf).

How should I connect the target? Why does connection to ML310 fail?
Ref: 0234

For connecting to the target use the included adapter together with the debug cable. The adapter plugs into the 14-pin connector of the target board. This port is also used to configure the FPGAs via the Xilinx download cable and often labelled as "FPGA&CPU Debug" or "PC4 JTAG".
For debugging Microblaze on Xilinx EVB ML310 always use the "PC4 JTAG" connector. The "CPU JTAG" connector will not work.
NOTE: Even though Microblaze and PPC405 use the same debug cable there is a difference regarding target connections: Microblaze cores are always debugged via the 14 pin header, whereas PPC405 cores (embedded in some Xilinx FPGAs) are occasionally accessed via other connectors.

I have problems loading C++ programs for Microblaze. Which parameters do I need?
Ref: 0272

For loading C++ programs for Microblaze that were generated with the Xilinx Tool chain use the Data.Load.ELF command with the parameters /cygdrive /gcc3 /gnucpp Data.Load.ELF command with the parameters /CYGDRIVE /GCC3 /GNUCPP

In some cases it is necessary to execute the sYmbol.CLEANUP command (no parameters) after loading the .elf file.


Data.LOAD.Elf filename.elf /CYGDRIVE /GCC3 /GNUCPP

MB V4.00.a: OnChip Data Breaks do not work as expected
Ref: 0238

Microblaze MB V4.00.a has a hardware issue that affects use of on-chip breaks. When specifying a read or write data value, the OnChip break logic does not consider the width of the access. Therefore avoid using the /DATA.Byte, /DATA.Word, /DATA.Long options. Simple read/write on-chip breaks that do not specify a data value work.
The hardware issue is fixed in MB V5.00.b.

Single stepping sometimes fails with MB V4.00.a, MB V5.00.A. What can I do?
Ref: 0237

In MicroBlaze V4.00.a, V5.00.A there is a hardware issue that can lead to erroneous single stepping behavior. Solution: update to TRACE32 from December 2006 or later. This release works around the problem.

The debugger does not display the source code associated with my program?
Ref: 0236

The Xilinx Microblaze compiler is based on the GNU GCC and the Cygwin toolset. Therefore file paths in the debug information in the .ELF file are generated in a non-standard form e.g. as /cygdrive/c/sample instead of
Use the option /CYGDRIVE for enabling automatic path conversion:
Data.LOAD.ELF MBSample/sample.elf /CYGDRIVE

Why are local variables displayed incorrectly?
Ref: 0391

When compiling MicroBlaze applications for debugging them with TRACE32, be sure to use the correct compiler options. The option "-g3" and DWARF2 debug info are recommended.

Note: The option "-g" creates debug info that is mostly intended for GDB and does not work well with TRACE32. The debugger will no be able to correctly display local variables, stack back trace etc.

Why are the on-chip databreaks unaligned with memory?
Ref: 0239

There is a (mostly theoretical) problem with the on-chip breakpoint implementation in MBV4, MBV5 related to unaligned memory accesses. A "sw" or "lw" instruction (store word, load word) writing/reading address 0x2003 will automatically word-align its address to 0x2000 before executing. However, an on-chip breakpoint set at 0x2000 will _not_ detect this access. The case is largely theoretical because the MB compiler does not create this kind of access. If necessary, the problem can be worked-around by using an address range for the OnChip as in "break.set 0x2000--0x2003 /read". (Note the "--" double minus for range specifiation).

Why do I get the message Warning: file [...]\gcc\libgloss\microblaze\crt0.S not found.
Ref: 0400

When creating programs with Xilinx EDK, the tool links some standard libraries with your code to create the executable. These standard libraries are built from files like crt0.S, crtinit.S etc. As they are created by Xilinx, the debug info contains paths to the source files specific to the Xilinx build machines. Usually these paths are not consistent with those on your machine.

To avoid the warning you can use the command sYmbol.SourcePATH.Translate to have TRACE32 look in a different directory for the source file. To find out the paths associated with the currently loaded program use the command. sYmbol.List.SOURCE


sYmbol.SourcePATH.TRANSLATE "\proj\epdsw\gnu\mb_gnu\src\gcc\libgloss\microblaze" "c:\Xilinx\14.4\ISE_DS\EDK\sw\lib\microblaze\src"

Why do software breakpoints or single stepping fail with uCLinux for MicroBlaze?
Ref: 0259

Because the initialization code for uCLinux overwrites the breakpoint handler, single stepping and software breakpoints will fail after starting the uCLinux kernel.
Use the command
SYStem.Option BrkVector 0x70
to specify an alternative location for the breakpoint handler.

Why does the Go.Up command fail inside interrupt handlers?
Ref: 0241

The Go.Up command (function key F6) may fail inside an interrupt, exception or break handler that is called via the brk or brki instructions. Use go.return to get to the end of the handler routine and leave it via step.asm until the PC is back in the interrupted routine.

Why does the setting of register R0 fail?
Ref: 0240

The architectural register R0 in Microblaze is hardcoded to 0. Therefore changing the register value to other values will fail.

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Last generated/modified: 02-Jan-2023