FAQs Archive for CPU32 Debugger
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Is my 68K ICD Debugger prepared for 3.3 V support? (68K)
Ref: 0111

All CPU specific ICD dongle after 07.98 with a serial number like 9807000xxxx with xxxx greater than 3000 support 3.3 V CPUs.
The JTAG/BDM input signals to the CPU will be driven with the same voltage detected on the VCCS pin.

Sometimes I receive the error message: "DTACK error reported by CPU" after the execution of the SYStem.Up command. (683XX)
Ref: 0039

After reset the CPU fetches first the stack pointer and the PC. If the fetched PC value is invalid it is impossibe to enter debug mode in the normal way. In this case the debugger asserts the BERR line on the BDM connector to enter debug mode. This special debug mode entry is indicated by the warning 
DTACK error reported by CPU
This is only a warning and you can continue to work as usual.

What can I do to emulate the M68360 QUADS Board with the BDM Debugger? (68360)
Ref: 0015

The watchdogs of both QUICCs are active after the execution of the SYStem.Up command. The master QUICC is immediately after RESET in debug mode, but the periphery of the slave will continue to run. So you have about 1 s until the watchdog of the slave will become active. You must use this second to disable this watchdog. There are two possibilities:
1. If you use the original boot EPROM: 
  SYStem.Up
  Go
  WAIT 1.0s
  Break
2. If you have no boot EPROM 
  SYStem.Up
; init Master MBAR
  Data.Set cpu:3ff00 %Long 0x00020001
; init Slave MBAR
  Data.Set cpu:3ff08 %Word 0xbfff
  Data.Set cpu:3ff04 %Word 0x0002
  Data.Set cpu:3ff08 %Word 0xbfff
  Data.Set cpu:3ff06 %Word 0x2001
  Data.Set sd:23022 %Byte 0x37
; disable Master WD
  Data.Set sd:21022 %Byte 0x37
; disable Slave WD
  Data.Set sd:23022 %Byte 0x37





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