MEET US @ embedded world 2022

Lauterbach has simplified the debugging of asynchronous multiprocessing systems with the innovative iAMP (integrated Asymetrical Multiprocessing) concept. The iAMP mode of Lauterbach’s TRACE32^® PowerView allows the integration of all debugger instances into a single view offering a highly improved user experience. This is a great advantage for systems with a larger number of identical cores, that are managed by different operating systems.

For more information download our iAMP application note.

Lauterbach is the leading provider of debug and trace solutions within the Arm^® ecosystem. The Lauterbach solutions support all important Arm^® processors like Cortex^®-M, Cortex^®-R, Cortex^®-A, Cortex^®-X, Neoverse^™ and SecurCore^®, as well as processors based on the new Arm^®v9 architecture.

Learn more about our Arm^® support

Virtualization is becoming increasingly important in embedded computing, in particular where safety and real-time behavior of the system is essential but cost saving pressures make it necessary to run several applications on a single hardware platform. To debug such a system or analyze its timing behavior, it is essential that the debugger is aware of the hypervisor and can distinguish between virtual machines and operating systems. TRACE32^® from Lauterbach is the only available JTAG debugging and tracing solution providing visibility of the whole software stack.

Learn more about Hypervisor-aware debugging

As a member of the AUTOSAR consortium, Lauterbach is active at the forefront of profiling solutions for the AUTOSAR Classic and Adaptive Platforms. We offer the broadest range of architecture support with a future-proof, Hypervisor-aware debugging and tracing solution. For in-depth analysis like event-chain-analysis, trace data can be imported into third-party timing verification tools.

Learn more about AUTOSAR profiling

As a leading provider of embedded software debug and trace tools, Lauterbach already supports processors based on the RISC-V instruction-set. At embedded world, we will showcase a multi-core trace scenario, with OS awareness, based on the upcoming Nexus trace standard.

Learn more about RISC-V debugging