32 Bit Emulation Controller
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Symbolic DebuggingA hierarchical symbol database enables structured symbolic debugging. Symbol names can be up to 255 significant characters long and can be used to show single program addresses, module names and memory classes. With 6 Mbyte of free memory (within the System Control Unit), approximately 200000 symbols may be loaded. The disassembler can use the symbols for labels and/or operands.
High-Level Language DebuggingThe high-level debugger can support all common high-level languages but includes special support for C and PASCAL in that it recognizes and uses all data types. The screen display can be in assembler, high-level or a mixture of the two. It is possible to construct both assembler and high-level windows on the screen simultaneously. All variable types specific to the high-level language can be displayed and modified. Addresses can be absolute, relative or line number based.
Real-Time DebuggingA newly developed multitasking debugger is provided which allows up to 16 processes or independent programs to be run simultaneously. Each task can be defined as a foreground or background task. For systems that require certain aspects of their operation to be maintained at all times (e.g. interrupts, timer operations etc), the background programs can be executed so that these real-time dependencies can be serviced. The foreground task is then debugged in the normal manner but even when not executing the foreground task, the background programs still operate in real-time.
Edit/Debug LinkThe editor window can be synchronised to the debugging window so that when an error is found, the source text can immediately be shown and if required, edited. Also during debugging, it is possible to place markers in the source text at appropriate points so that all corrections can be made at the same time, but later. When the source text is re-opened, the system will present each line marked for correction in sequence.
On-Screen AssemblerThe on-screen assembler is provided in place of the more common line assembler found on other systems. With the on-screen assembler, short programs can be written quickly and reliably. It is a full assembler whose output code is linkable in the usual way to the main body of the program.
Separate Emulation Control ProcessorThe emulator is controlled by a separate processor with approximately 1 MIPs performance. Functions such as task changing or memory refresh are done independently of the main system controller or the emulation CPU.
2 Emulator Operating Modes
Multi-Step OperationA step mode is provided whereby the emulator simply steps the CPU instruction by instruction as fast as it can. In this mode, operating speed of the target is reduced by a factor of approximately 100, but all register values are available at each step.
Bus Structure for 64 Bit EmulationThe emulation bus is 64 bit wide in order to support future processors.
High Clock FrequencyBecause of the compact, layered construction, bus lengths are kept to a minimum and clock frequencies of 50MHz are possible for the support of fast 32 bit CPUs.
Memory Orientated Breakpoint System with up to 16 Mbyte Breakpoint MemoryMost currently available emulators use multiple address and data comparators to form the breakpoint system. This technique not only restricts the number of breakpoints available it also means that systems using bank selection are difficult to support. The breakpoint, memory on the TRACE32 is basically a bytewide memory structure that can be mapped in a similar way to the overlay memory. When any memory location is accessed, the corresponding breakpoint byte is also accessed so that there are effectively 8 kinds of breakpoints for each addressable location.
8 Breakpoint Types
Hardware Support for High-Level Language DebuggingBy using a specially reserved bit in the breakpoint memory, high-speed debugging of systems using high-level languages is available.
Memory Test on Power up with Access Time TestAfter turning on the system, an optional memory test can be performed on both emulation and breakpoint memories.
Support for External Bank Switching (up to 256 banks)External bank switching schemes or MMUs can be supported by the memory mapper. For this there are separate probe inputs to the emulator. This option is only sensible on CPUs with less than 16 Mbyte addressing range.
Support for EPROMs with Inbuilt PagingEPROMs of the types 27513 or 27011 are supported without external logic. The address area within the EPROM has to be defined by the user, so that the emulator can support the device.
Support for Dynamic Memory in the Target SystemIn order to refresh target dynamic RAM when the emulation is stopped, a memory refresh function is provided. The address range and memory class over which the refresh occurs can be defined.
Selective Mapping of Memory Classes (Memory, I/O, User, Data etc.)The address mapper can segment the memory into 4 segments. Using this segmentation, it is possible for example to split the memory such that a USER area can be mapped to the emulators ram whilst the SUPERVISORY area remains mapped as target memory. It is also possible to have totally separate physical memory areas displayed simultaneously.
Memory Mapping in 4K Blocks and bytewiseThe main mapping of memory is done in 4K blocks. However within two address ranges 16K long mapping can also be performed down to a single byte resolution (useful for I/O mapping).
Memory Mapping Functions
Wait States0 to 250 wait cycles can be specified within any particular address range.
Access Protection and Write ProtectionData access in specific address areas can be prevented. Using this feature for example, it is possible to prevent an I/O access occurring at a specific address (if bytewise mapping is operative).
Most Emulation Functions can be used whilst the target CPU is running ('on the fly' operation)
Dual-Ported Access to All Emulation MemoryThe whole emulation memory system (emulation and breakpoint memory) in dual-ported. This allows the emulator to read or write memory whilst the target system is running in real-time e.g. to show variables, port contents etc. For low to medium speed CPU clock frequencies (e.g. 12MHz 68000) there is no degradation in performance of the target system due to the operation of the dual-port access mechanism. At higher CPU clock frequencies, the performance may be slightly reduced in accordance with the number of accesses made by the control system. The dual-port access mechanism can be switched off, but if this is done, then memory access by the emulator can only take place when the target system is stopped.
Maximum 16 Mbyte Emulation RAM and 16 Mbyte Breakpoint RAMIn order to store programs in the emulator during the development phase, the address space of the emulator can be as high as 16 Mbyte. This memory can be implemented using static or dynamic rams.
2 Mbyte Emulation and Breakpoint Memory in the ECU ModuleIn the ECU module, up to 2 Mbyte of memory may be fitted. This can be user defined to be either emulation memory or breakpoint memory.
Flag SystemIn a special memory, all addresses which are read or written are marked with read or write flags. This memory therefore can supply a lot of important information:
External Trigger Inputs8 external inputs are provided which can be used as even trigger sources.
Trigger Outputs8 trigger/status outputs are provided. These outputs are mainly intended for triggering or controlling certain functions within the target system. External Analyzers can be triggered using the Trace Analyzer outputs.
Internal Frequency Generator
Integrated Universal Counter
Inbuilt GLITCH Detector for all important CPU Signals
Slave StopMaster/Slave Synchronisation of several Emulators and AnalyzersEach of the following functions can be enabled or disabled individually:
Runtime AnalyzerProgram runtime is recorded automatically.
Inbuilt Pulse Generator
Bus TimeoutCycle time programmable from 10 us to 10s. Expiry of the timeout period can be made to generate an emulator break.
Clock Monitor for Target SystemIf the clock period becomes bigger 10us the system will alert the user. If programmed to do so, the emulator can go into a standby mode if this occurs.
Conditional BreakpointsIn each breakpoint group a PASS count can be specified.
Trigger Event StorageIndependently of any analyzer functions, the addresses or address range, status and trigger source of each trigger event can be stored.
Delayed TriggeringA trigger delay between the trigger event and the emulation break can be specified in terms of time, a cycle count or trace cycle count.
Trigger Event Sources
Event TriggeringEach of the above trigger events can be selected as the source for the event triggering. The following trigger modes are possible:
Access CounterEach of the general purpose address breakpoints A, B & C has an associated 48 bit counter. Using these it is possible for example to count the number of accesses to specific variables within an address range before a trigger is generated.
Trigger MonitorThe status of all the trigger settings are visible within their own window and can be modified `on the fly`.
Static Memory Modules
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Last generated/modified: 06-May-2019